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參數(shù)資料
| 型號： | DS3112N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 46/134頁 |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
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DS3112
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2.3 T3 / E3 RECEIVE FRAMER SIGNAL DESCRIPTION
Signal Name:
FRSOF
Signal Description:
T3/E3 Receive Framer Start Of Frame Sync Signal
Signal Type:
Output
This signal pulses for one FRCLK period to indicate the T3 or E3 frame boundary. See Figure 2.3A for
an example. This signal can be configured via the FRSOFI control bit in Master Control Register 3 (see
Section 4.2) to be either active high (normal mode) or active low (inverted mode).
Signal Name:
FRCLK
Signal Description:
T3/E3 Receive Framer Clock
Signal Type:
Output
This signal outputs the clock that is used to pass data through the receive T3/E3 framer. It can be sourced
from either the HRCLK or FTCLK inputs (see Figures 1A and 1B for details). This signal is used to
clock the receive data out of the device at the FRD output. Data can be either updated on a rising edge
(normal mode) or a falling edge (inverted mode). This option is controlled via the FRCLKI control bit in
Master Control Register 3 (see Section 4.2).
Signal Name:
FRD
Signal Description:
T3/E3 Receive Framer Serial Data
Signal Type:
Output
This signal outputs data from the receive T3/E3 framer. This signal is updated either on the rising edge
of FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). This option is controlled via
the FRCLKI control bit in Master Control Register 3 (see Section 4.2). Also, this signal can be internally
inverted if enabled via the FRDI control bit in Master Control Register 3 (see Section 4.2).
Signal Name:
FRDEN
Signal Description:
T3/E3 Receive Framer Serial Data Enable or Gapped Clock Output
Signal Type:
Output
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a
data enable or a gapped clock. In the data enable mode, this signal will go active when payload data is
available at the FRD output and it will go inactive when overhead data is being output at the FRD output.
In the gapped clock mode, this signal will transition for each bit of payload data and will be suppressed
for each bit of overhead data. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X
Bits, and P Bits. In the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e. bits
1 to 12). See Figure 2.3A for an example. This signal can be internally inverted if enabled via the
FRDENI control bit in Master Control Register 3 (see Section 4.2).
Signal Name:
FRMECU
Signal Description:
T3/E3 Receive Framer Manual Error Counter Update Strobe
Signal Type:
Input
Via the AECU control bit in Master Control Register 1 (see Section 4.2), the DS3112 can be configured
to use this asynchronous input to initiate an updating of the internal error counters. A 0 to 1 transition on
this input causes the device to begin loading the internal error counters with the latest error counts. This
signal must be returned low before a subsequent updating of the error counters can occur. The Host must
wait at least 100 ns before reading the error counters to allow the device time to update the error counters.
This signal is logically OR’ed with the MECU control bit in Master Control Register 1. If this signal is
not used, then it should be tied low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3112 | DATACOM, FRAMER, PBGA256 |
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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