參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 95/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
63 of 134
Bits 0 to 15 / 16-Bit T3 C-Bit Parity Bit Error Counter (CPE0 to CPE15). These bits report the
number of T3 C-Bit Parity Bit errors. When the device is not in the C-Bit parity Mode or when the
device is in the E3 Mode, this counter is meaningless and should be ignored. A C-Bit Parity Bit error is
defined as an occurrence when the majority decoded three CP Parity Bits do not match the parity
calculation made on the information bits. Via the ECC control bit in the T3/E3 Control Register (see
Section 5.2), the CPCR can be configured to either continue counting C-Bit parity bit errors during a LOF
or not.
Register Name:
FEBECR
Register Description:
T3 Far End Block Error or E3 RAI Count Register
Register Address:
2Ah
Bit #
765
43210
Name
FEBE7
FEBE6
FEBE5
FEBE4
FEBE3
FEBE2
FEBE1
FEBE0
Default
---
-----
Bit #
151413
121110
9
8
Name
FEBE15
FEBE14
FEBE13
FEBE12
FEBE11
FEBE10
FEBE9
FEBE8
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 15 / 16-Bit T3 Far End Block Error or E3 RAI Counter (FEBE0 to FEBE15). In the T3 C-
Bit Parity Mode, these bits report the number of T3 Far End Block Errors (FEBE). This counter
increments each time the three FEBE bits do not equal 111. In the E3 Mode, these bits report the number
of times the RAI bit is received in the “disturbed state” (i.e. the number of times that it is set to a one). In
the T3 mode, when the device is not in the C-Bit parity Mode, this counter is meaningless and should be
ignored. Via the ECC control bit in the T3/E3 Control Register (see Section 5.2), the FEBECR can be
configured to either continue counting FEBEs or active RAI bits during a LOF or not.
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