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| 型號(hào)： | DS3112N |
| 廠(chǎng)商： | DALLAS SEMICONDUCTOR |
| 元件分類(lèi)： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 84/134頁(yè) |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
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DS3112
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5.3 T3 / E3 FRAMER STATUS and INTERRUPT REGISTER DESCRIPTION
Register Name:
T3E3SR
Register Description:
T3/E3 Status Register
Register Address:
12h
Bit #
765
43210
Name
n/a
RSOF
TSOF
T3IDLE
RAI
AIS
LOF
LOS
Default
---
-----
Bit #
151413
121110
9
8
Name
n/a
Default
---
-----
Note: See Figure 5.3A for details on the signal flow for the status bits in the T3E3SR register.
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Loss Of Signal Occurrence (LOS). This latched read only alarm status bit will be set to a one
when the T3 or E3 framer detects a loss of signal. This bit will be cleared when read unless a LOS
condition still exists. A change in state of the LOS can cause a hardware interrupt to occur if the LOS bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt
Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is
read. The LOS alarm criteria is described in Tables 5.3A and 5.3B
Bit 1 / Loss Of Frame Occurrence (LOF). This latched read only alarm status bit will be set to a one
when the T3 or E3 framer detects a loss of frame. This bit will be cleared when read unless a LOF
condition still exists. A change in state of the LOF can cause a hardware interrupt to occur if the LOF bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt
Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The LOF alarm criteria is described in Tables 5.3A and 5.3B
Bit 2 / Alarm Indication Signal Detected (AIS). This latched read only alarm status bit will be set to a
one when the T3 or E3 framer detects an incoming Alarm Indication Signal. This bit will be cleared
when read unless an AIS signal is still present. A change in state of the AIS detection can cause a
hardware interrupt to occur if the AIS bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a
one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read. The AIS alarm detection criteria is described in Tables 5.3A and
5.3B
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PDF描述 |
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| DS3112 | DATACOM, FRAMER, PBGA256 |
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| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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