- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97869 > DS3112N (DALLAS SEMICONDUCTOR) DATACOM, FRAMER, PBGA256 PDF資料下載
參數(shù)資料
| 型號： | DS3112N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 90/134頁 |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁
DS3112
59 of 134
Bit 2 / F Bit or FAS Error Detected (FBE). This latched read only status bit will be set to a one when
the DS3112 has detected an error in either the F Bits (T3 mode) or the FAS word (E3 mode). This bit
will be cleared when read and will not be set again until the device detects another error.
Bit 3 / M Bit Error Detected (MBE). This latched read only event status bit will be set to a one when
the DS3112 has detected an error in the M Bits. This bit will be cleared when read and will not be set
again until the device detects another error in one of the M Bits. This status bit has no meaning in the E3
mode and should be ignored.
Bit 4 / EXcessive Zeros Detected (EXZ). This latched read only event status bit will be set to a one
each time the DS3112 has detected a consecutive string of either 3 or more zeros (T3 mode) or 4 or more
zeros (E3 mode). This bit will be cleared when read and will not be set again until the device detects
another EXcessive Zero event.
Bit 5 / Severely Errored Framing Event Detected (SEFE). This latched read only event status bit will
be set to a one each time the DS3112 has detected either 3 or more F Bits in error out of 16 consecutive F
Bits (T3 mode) or four bad FAS words in a row (E3 mode). This bit will be cleared when read and will
not be set again until the device detects another SEFE event.
Bit 8 / E3 National Bit (E3Sn). This read only real time status bit reports the incoming E3 National Bit
(Sn). It is loaded at the start of each E3 frame as the Sn bit is decoded. The Host can use the RSOF
status bit in the T3/E3 Status Register (T3E3SR) to determine when to read this bit.
Bit 9 / T3 Application ID Channel Status (T3AIC). This read only real time status bit can be used to
help determine whether an incoming T3 data stream is in C-Bit Parity mode or M23 mode. In C-Bit
Parity mode, it is recommended that the first C Bit in each M Frame be set to one. In M23 mode, the first
C Bit in each M frame should be toggling between 0 and 1 to indicate that the bits need to be stuffed or
not. This bit will be set to a one when the device detects that the first C Bit in the M Frame is set to one
for 1020 times or more out of 1024 consecutive M Frames (109ms). It will be allowed to be cleared
when the device detects that the first C Bit is set to one less than 1020 times out of 1024 consecutive M
Frames (109ms). This status bit has no meaning in the E3 mode and should be ignored.
Bit10 / Loss Of Signal Clear Detected (LOSC). This latched read only event status bit will be set to a
one each time the T3/E3 framer exits a Loss Of Signal (LOS) state. This bit will be cleared when read
and will not be set again until the device once again exits the LOS state. The LOS alarm criteria is
described in Tables 5.3A and 5.3B. This status bit is useful in helping the Host determine if the LOS
persists as defined in ANSI T1.231.
Bit11 / Loss Of Frame Clear Detected (LOFC). This latched read only event status bit will be set to a
one each time the T3/E3 framer exits a Loss Of Frame (LOF) state. This bit will be cleared when read
and will not be set again until the device once again exits the LOF state. The LOF alarm criteria is
described in Tables 5.3A and 5.3B. This status bit is useful in helping the Host determine if the LOF
persists as defined in ANSI T1.231.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3112 | DATACOM, FRAMER, PBGA256 |
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。