參數(shù)資料
型號(hào)： DS3112N
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 83/134頁
文件大?。?/td> 900K
代理商： DS3112N
DS3112
52 of 134
Bit 3 / T3 C-Bit Parity Error Insert (T3CPBEI). A 0 to 1 transition on this bit will cause a single T3
C-Bit Parity error event to be inserted into the transmit data stream. A T3 Parity event is defined as
flipping the proper polarity of all three CP Bits in a T3 Frame (see Section 15.2 for details about the CP
Bits). Once this bit has been toggled from a 0 to a 1, the device waits for the next T3 frame to flip the
three CP Bits. This bit must be cleared and set again for a subsequent error to be inserted. Toggling this
bit has no affect when the T3 framer is not operated in the C-Bit Parity Mode (see Section 4.2 for details
about the C-Bit Parity Mode) or when the device is operated in the E3 Mode. In the Manual Error Insert
mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is
set high. When this bit is set low, no errors will be inserted.
Bit 4 / Frame Bit Error Insert (FBEI). A 0 to 1 transition on this bit will cause the transmit framer to
generate framing bit errors. The type of framing bit errors inserted is controlled by the FBEIC0 and
FBEIC1 bits (see discussion below). Once this bit has been toggled from a 0 to a 1, the device waits for
the next possible framing bit to insert the errors. This bit must be cleared and set again for a subsequent
error to be inserted. In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle
of the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be
inserted.
Bits 5 and 6 / Frame Bit Error Insert Control Bits 0 and 1 (FBEIC0 and FBEIC1).
FBEIC1
FBEIC0
Type Of Framing Bit Error Inserted
00
T3 Mode: a single F-Bit error
E3 Mode: a single FAS word of 1111000000 is generated instead of the
normal FAS word which is 1111010000 (i.e. only 1 bit inverted)
01
T3 Mode: a single M-Bit error
E3 Mode: a single FAS word of 0000101111 is generated instead of the
normal FAS word which is 1111010000 (i.e. all FAS bits are inverted)
10
T3 Mode: 4 consecutive F-Bit errors (causes the far end to lose
synchronization)
E3 Mode: 4 consecutive FAS words of 1111000000 are generated
instead of the normal FAS word which is 1111010000 (i.e. only 1 bit
inverted; causes the far end to lose synchronization)
11
T3 Mode: 3 consecutive M-Bit errors (causes the far end to lose
synchronization)
E3 Mode: 4 consecutive FAS words of 0000101111 are generated
instead of the normal FAS word which is 1111010000 (i.e. all FAS bits
are inverted; causes the far end to lose synchronization)
Bit 7 / Manual Error Insert Mode Select (MEIMS). When this bit is set low, the device will insert
errors on each 0 to 1 transition of the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits. When this
bit is set high, the device will insert errors on each 0 to 1 transition of the FTMEI input signal. The
appropriate BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bit must be set to one for this to occur. If
all of the BPVI, EXZI, T3PBEI, T3CPBEI, and FBEI control bits are set to zero, no errors are inserted.
0 = use 0 to 1 transition on the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits to insert errors
1 = use 0 to 1 transition on the FTMEI input signal to insert errors
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