參數(shù)資料
型號(hào): DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 65/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
36 of 134
Register Name:
MC3
Register Description:
Master Configuration Register 3
Register Address:
06h
Bit #
765
43210
Name
FRSOFI
FRCLKI
FRDI
FRDENI
FTSOFI
FTCLKI
FTDI
FTDENI
Default
000
00000
Bit #
151413
121110
9
8
Name
n/a
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / FTDEN Invert Enable (FTDENI).
0 = do not invert the FTDEN signal (normal mode)
1 = invert the FTDEN signal (inverted mode)
Bit 1 / FTD Invert Enable (FTDI).
0 = do not invert the FTD signal (normal mode)
1 = invert the FTD signal (inverted mode)
Bit 2 / FTCLK Invert Enable (FTCLKI).
0 = do not invert the FTCLK signal (normal mode)
1 = invert the FTCLK signal (inverted mode)
Bit 3 / FTSOF Invert Enable (FTSOFI).
0 = do not invert the FTSOF signal (normal mode)
1 = invert the FTSOF signal (inverted mode)
Bit 4 / FRDEN Invert Enable (FRDENI).
0 = do not invert the FRDEN signal (normal mode)
1 = invert the FRDEN signal (inverted mode)
Bit 5 / FRD Invert Enable (FRDI).
0 = do not invert the FRD signal (normal mode)
1 = invert the FRD signal (inverted mode)
Bit 6 / FRCLK Invert Enable (FRCLKI).
0 = do not invert the FRCLK signal (normal mode)
1 = invert the FRCLK signal (inverted mode)
Bit 7 / FRSOF Invert Enable (FRSOFI).
0 = do not invert the FRSOF signal (normal mode)
1 = invert the FRSOF signal (inverted mode)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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