參數(shù)資料
型號： DS3112N
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 53/134頁
文件大?。?/td> 900K
代理商： DS3112N
DS3112
25 of 134
Signal Name:
LTDATA / LTDATB
Signal Description:
Low Speed (T1 or E1) Transmit Insert Port Serial Data Inputs
Signal Type:
Input
These two input signals allow data to be inserted in place of any of the 28 T1 data streams or into any of
the 16/21 E1 data streams (see Section 7.4). Data can be clocked into the device either on falling edges
(normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This option is
controlled via the LTCLKI control bit in Master Control Register 2 (see Section 4.2). Also, the data can
be internally inverted before being multiplexed if enabled via the LTDATI control bit in Master Control
Register 2 (see Section 4.2). When the M13 / E13 multiplexer is disabled, then these inputs are ignored
and should be tied low.
Signal Name:
LTCLKA / LTCLKB
Signal Description:
Low Speed (T1 or E1) Transmit Insert Port Serial Clock Inputs
Signal Type:
Input
These two input signals are used to clock data into the device that will be inserted into one of the 28 T1
data streams or into one of the 16/21 E1 data streams (see Section 7.4). The T1 or E1 serial data streams
at the associated LTDAT signals can be clocked into the device either on falling edges (normal clock
mode) or rising edges (inverted clock mode) of LTCLKA/LTCLKB. This option is controlled via the
LTCLKI control bit in Master Control Register 2 (see Section 4.2). When the M13 / E13 multiplexer is
disabled, then these inputs are ignored and should be tied low.
Signal Name:
LTCCLK
Signal Description:
Low Speed (T1 or E1) Transmit Common Clock Input
Signal Type:
Input
If enabled via the LTCCEN in Master Control Register 1 (see Section 4.2), all 28 LTCLK or 16 LTCLK
signals are disabled and all the data at the 28 LTDAT or 16 LTDAT inputs (as well as the LTDATA and
LTDATB inputs) will be clocked into the device using the LTCCLK signal. In T3 mode, LTCCLK
would be a 1.544 MHz clock and in E3 mode, LTCCLK would be 2.048 MHz. If not used, this signal
should be tied low. If this signal is used, then all of the LTCLK signals should be tied low. This signal
can be internally inverted. This option is controlled via the LTCLKI control bit in Master Control
Register 2 (see Section 4.2).
相關(guān)PDF資料
PDF描述
DS3112 DATACOM, FRAMER, PBGA256
DS3131 SPECIALTY TELECOM CIRCUIT, PBGA256
DS3134 DATACOM, FRAMER, PBGA256
DS3150QN DATACOM, PCM TRANSCEIVER, PQCC28
DS3150Q DATACOM, PCM TRANSCEIVER, PQCC28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS3112RD 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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