參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 115/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
81 of 134
SECTION 8: BERT
8.1 GENERAL DESCRIPTION
The BERT Block is capable of generating and detecting the following patterns:
- the pseudorandom patterns 2^7 – 1, 2^11 – 1 , 2^15 – 1 , and QRSS
- a repetitive pattern from 1 to 32 bits in length
- alternating (16-bit) words which flip every 1 to 256 words
The BERT receiver has a 32-bit Bit Counter and a 24-bit Error Counter. It can generate interrupts on
detecting a bit error, a change in synchronization, or if an overflow occurs in the Bit and Error Counters.
See Section 8.2 for details on status bits and interrupts from the BERT Block. To activate the BERT
Block, the Host must configure the BERT mux via the BERT Mux Control register (see Section 8.2).
Data can be routed to the receive side of the BERT from either the T3/E3 framer or from one of the 28 T1
or 16/21 E1 receive ports. Data from the transmit side of the BERT can be inserted either into the T3/E3
framer or into one of the 28 T1 or 16/21 E1 transmit ports. See Figures 1A and 1B for a visual
description of where data to and from the BERT can be placed.
8.2 BERT REGISTER DESCRIPTION
Register Name:
BERTMC
Register Description:
BERT Mux Control Register
Register Address:
0x6Eh
Bit #
765
43210
Name
n/a
RBPS4
RBPS3
RBPS2
RBPS1
RBPS0
Default
-
00000
Bit #
151413
121110
9
8
Name
n/a
TBPS4
TBPS3
TBPS2
TBPS1
TBPS0
Default
-
00000
Note: Bits that are underlined are read only; all other bits are read-write.
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