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參數(shù)資料
| 型號： | DS3112N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 126/134頁 |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
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DS3112
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Transmit Operation
On reset, the transmit HDLC controller will flush the transmit FIFO and transmit an abort followed by
either 7Eh or FFh (depends on the setting of the TFS control bit) continuously. The transmit HDLC then
waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The
transmit HDLC will automatically add an opening flag of 7Eh to the beginning of the packet and zero
stuff the outgoing datastream. When the transmit HDLC controller detects that the TMEND bit in the
transmit FIFO is set, it will automatically calculate and add in the 16-bit CRC checksum followed by a
closing flag of 7Eh. If the FIFO is empty, then it will begin sending either 7Eh or FFh continuously. If
there is some more data in the FIFO, then the transmit HDLC will automatically add in the opening flag
and begin sending the next packet. Between consecutive packets, there are always at least two flags of
7Eh. If the transmit FIFO ever empties when a packet is being sent (i.e. before the TMEND bit is set),
then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a
continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR)
status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the
Host.
The transmit HDLC has been designed to minimize it’s real time Host support requirements. The
transmit FIFO is 256 bytes which is deep enough to store the three T3 packets (Path ID, Idle Signal ID,
and Test Signal ID) that need to be sent once a second. Hence in T3 applications, the Host only needs to
access the transmit HDLC once a second to load up the three messages. Once the Host has loaded an
outgoing packet, it can monitor the Transmit Packet End (TEND) status bit to know when the packet has
finished being transmitted.
Also the Host can be notified when the FIFO has emptied below a
programmable level called the low water mark. The Host must never overfill the FIFO. To keep this
from occurring, the Host can obtain the real time depth of the transmit FIFO via the Transmit FIFO Level
bits in the HDLC Status Register (HSR).
9.2 HDLC CONTROL AND FIFO REGISTER DESCRIPTION
Register Name:
HCR
Register Description:
HDLC Control Register
Register Address:
80h
Bit #
7
654
321
0
Name
n/a
RHR
THR
TFS
n/a
TCRCI
TZSD
TCRCD
Default
-
000
-
0
Bit #
15
14
13
12
11
10
9
8
Name
RHWMS2 RHWMS1
RHWMS0
TLWMS2
TLWMS1
TLWMS0 RID
TID
Default
0
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Transmit CRC Defeat (TCRCD). When this bit is set low, the HDLC will automatically
calculate and append the 16 bit CRC to the outgoing HDLC message. When this bit is set high, the
device will not append the CRC to the outgoing message.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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