參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 78/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
48 of 134
5.2 T3 / E3 FRAMER CONTROL REGISTER DESCRIPTION
Register Name:
T3E3CR
Register Description:
T3/E3 Control Register
Register Address:
10h
Bit #
7
6
5
4
3
2
1
0
Name
DLB
LLB
T3IDLE
E3SnC1
E3SnC0
TPT
TRAI
TAIS
Default
0
Bit #
15
1413
1211
10
9
8
Name
n/a
PLB
TFEBE
AFEBED
ECC
FECC1
FECC0
E3CVE
Default
-
00
0
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / T3/E3 Transmit Alarm Indication Signal (TAIS). When this bit is set high in the T3 Mode, the
transmitter will generate a properly F-Bit and M-Bit framed 101010... data pattern with both X Bits set to
one, all C bits set to zero, and the proper P Bits. This is true regardless of whether the device is in the C-
Bit Parity Mode or not. When this bit is set high in the E3 Mode, the transmitter will generate an
unframed all ones. When this bit it set low, normal data is transmitted.
0 = do not transmit AIS
1 = transmit AIS
Bit 1 / T3/E3 Transmit Remote Alarm Indication (TRAI). When this bit is set high in the T3 Mode,
both X Bits will be set to a zero. When this bit is set high in the E3 Mode, the RAI bit (bit number 11 of
each E3 frame) will be set to a one. When this bit it set low in the T3 Mode, both X Bits will be set to
one. When this bit is set low in the E3 Mode, the RAI bit will be set to a zero.
0 = do not transmit RAI
1 = transmit RAI
Bit 2 / T3/E3 Transmit Pass Through Enable (TPT).
0 = enable the framer to insert framing and overhead bits
1 = framer will not insert any framing or overhead bits
Bits 3 and 4 / E3 National Bit Control Bits 0 and 1 (E3SnC0 and E3SnC1). These bits determine
where the E3 National bit is sourced from. On the receive side, the Sn bit is always routed to the
T3E3INFO Register as well as the HDLC controller and the FEAC controller. These bits are ignored in
the T3 Mode.
E3SnC1
E3SnC0
Source of the E3 National Bit (Sn)
0
force the Sn bit to one
0
1
use the HDLC controller to source the Sn bit
1
0
use the FEAC controller to source the Sn bit
1
force the Sn bit to zero
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相關(guān)代理商/技術(shù)參數(shù)
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