參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 117/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
83 of 134
TBPS4:0
10100 Port 20
11100 Port 28
10101 Port 21
11101 T3/E3 Framer (payload bits only)
10110 Port 22
11110 T3/E3 Framer (payload + overhead bits)
10111 Port 23
11111 illegal state
Register Name:
BERTC0
Register Description:
BERT Control Register 0
Register Address:
70h
Bit #
765
432
1
0
Name
n/a
TINV
RINV
PS2
PS1
PS0
LC
RESYNC
Default
-
00
000
0
Bit #
151413
121110
9
8
Name
IESYNC
IEBED
IEOF
n/a
RPL3
RPL2
RPL1
RPL0
Default
000
-
0000
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Force Resynchronization (RESYNC). A low to high transition will force the receive BERT
synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high
whenever the Host wishes to acquire synchronization on a new pattern. Must be cleared and set again for
a subsequent resynchronization.
Bit 1 / Load Bit and Error Counters (LC). A low to high transition latches the current bit and error
counts into the Host accessible registers BERTBC and BERTEC and clears the internal count. This bit
should be toggled from low to high whenever the Host wishes to begin a new acquisition period. Must be
cleared and set again for a subsequent loads.
Bits 2 to 4 / Pattern Select Bits 0 (PS0 to PS2).
000 = Pseudorandom Pattern 2^7 – 1 (ANSI T1.403-1999 Annex B)
001 = Pseudorandom Pattern 2^11 – 1 (ITU O.153)
010 = Pseudorandom Pattern 2^15 – 1 (ITU O.151)
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = illegal state
111 = illegal state
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