參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 119/134頁
文件大小: 900K
代理商: DS3112N
DS3112
85 of 134
Register Name:
BERTC1
Register Description:
BERT Control Register 1
Register Address:
72h
Bit #
765
43210
Name
EIB2
EIB1
EIB0
SBE
n/a
TC
Default
-
00
00000
Bit #
151413
121110
9
8
Name
AWC7
AWC6
AWC5
AWC4
AWC3
AWC2
AWC1
AWC0
Default
000
00000
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Transmit Pattern Load (TC).
A low to high transition loads the pattern generator with
Repetitive or Pseudorandom pattern that is to be generated. This bit should be toggled from low to high
whenever the Host wishes to load a new pattern. Must be cleared and set again for a subsequent loads.
Bit 4 / Single Bit Error Insert (SBE). A low to high transition will create a single bit error. Must be
cleared and set again for a subsequent bit error to be inserted.
Bits 5 to 7 / Error Insert Bits (EIB0 to EIB2).
Will automatically insert bit errors at the prescribed rate into the generated data pattern. Useful for
verifying error detection operation.
EIB2
EIB1
EIB0
Error Rate Inserted
0
no errors automatically inserted
0
1
10^-1 (1 error per 10 bits)
0
1
0
10^-2 (1 error per 100 bits)
0
1
10^-3 (1 error per 1 kbits)
1
0
10^-4 (1 error per 10 kbits)
1
0
1
10^-5 (1 error per 100 kbits)
1
0
10^-6 (1 error per 1M bits)
1
10^-7 (1 error per 10M bits)
Bits 8 to 15 / Alternating Word Count Rate (AWC0 to AWC7). When the BERT is programmed in
the alternating word mode, the word in BERTRP0 will be transmitted for the count loaded into this
register plus one, then flip to the other word loaded in BERTRP1 and again repeat for the same number of
times. The valid count range is from 00h to FFh.
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