參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 66/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
37 of 134
4.3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION
A Note About The Status Registers in the DS3112
The status registers in the DS3112 allow the Host to monitor the real time condition of the device. Most
of the status bits in the device can cause a hardware interrupt to occur. Also, most of the status bits
within the device are latched to insure that the Host can detect changes in state and the true status of the
device. There are three types of status bits in the DS3112. The first type is called an event status bit and
it is derived from a momentary condition or state that occurs within the device. The event status bits are
always cleared when read and can generate an interrupt when they are asserted. An example of an event
status bit is the One Second Timer Boundary Occurrence (OST). The second type of status bit is called
an alarm status bit and it is derived from conditions that can occur for longer than an instance. The alarm
status bits will be cleared when read unless the alarm is still present. The alarm status bits generate
interrupts on a change in state in the alarm (i.e. when it is asserted or deasserted). An example of an
alarm status bit is the Loss Of Frame (LOF). The third type of status bit is called a real time status bit.
The real time status bit remains active as long as the condition exists and will generate an interrupt as
long as the condition exists. An example of a real time status bit is the Loss Of Transmit Clock (LOTC).
Event Status Bit Figure 4.3A
Alarm Status Bit Figure 4.3B
Internal Signal
Status Bit
Interrupt
Read
Internal Signal
Status Bit
Interrupt
Read
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