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參數(shù)資料
| 型號(hào)： | DS3112N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 125/134頁(yè) |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
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DS3112
90 of 134
SECTION 9: HDLC CONTROLLER
9.1 GENERAL DESCRIPTION
The DS3112 contains an onboard HDLC controller with 256 byte buffers in both the transmit and receive
paths. When the device is operated in the T3 Mode, the HDLC controller is only active in the C-Bit
Parity Mode. When the device is operated in the E3 mode, the user has the option to connect the HDLC
controller to the Sn bit position. On the receive side, the HDLC controller is always connected to the
receive E3 framer. If the Host does not wish to use the HDLC controller for the Sn bit, then the status
updates provided by the HDLC controller are ignored. On the transmit side, the Host selects the source
of the Sn via the E3SnC0 and E3SnC1 controls bits in the T3/E3 Control Register (see Section 5.2 for
details).
Receive Operation
On reset, the receive HDLC controller will flush the receive FIFO and begin searching for a new
incoming HDLC packet. The receive HDLC controller performs a bit by bit search for a HDLC packet
and when one is detected, it will zero destuff the incoming datastream and automatically byte align to it
and place the incoming bytes as they are received into the receive FIFO. The first byte of each packet is
marked in the receive FIFO by setting the Opening Byte (OBYTE) bit. Upon detecting a closing flag, the
device will check the 16-bit CRC to see if the packet is valid or not and then mark the last byte of the
packet in the receive FIFO by setting the Closing Byte (CBYTE) bit. The CRC is not passed to the
receive FIFO. When the CBYTE bit is set, the Host can obtain the status of the incoming packet via the
Packet Status bits (PS0 and PS1). Incoming packets can be separated by a single flag or even by two
flags that share a common zero. If the receive FIFO ever fills beyond capacity, the new incoming packet
data will be discarded and the Receive FIFO Overrun (ROVR) status bit will be set. If such a scenario
occurs, then the last packet in the FIFO is suspect and should be discarded. When an overflow occurs,
the receive HDLC will stop accepting packets until either the FIFO is completely emptied or reset. If the
receive HDLC controller ever detects an incoming abort (7 or more ones in a row), it will set the Receive
Abort Sequence Detected (RABT) status bit. If an abort sequence is detected in the middle of an
incoming packet, then the receive HDLC controller will set the Packet Status bits accordingly.
The receive HDLC has been designed to minimize it’s real time Host support requirements. The receive
FIFO is 256 bytes which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test
Signal ID) that can arrive once a second. Hence in T3 applications, the Host only needs to access the
receive HDLC once a second to retrieve the three messages. The Host will be notified when a new
message has begun (Receive Packet Start status bit) to be received and when a packet has completed
(Receive Packet End status bit). Also the Host can be notified when the FIFO has filled beyond a
programmable level called the high water mark. The Host will read the incoming packet data out of the
receive FIFO a byte at a time. When the receive FIFO is empty, the REMPTY bit in the FIFO will be set.
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PDF描述 |
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| DS3112 | DATACOM, FRAMER, PBGA256 |
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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