參數(shù)資料
型號(hào)： AD6652XBC
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 66/76頁(yè)
文件大?。?/td> 1802K
代理商： AD6652XBC
Preliminary Technical Data
AD6652
Rev. PrC | Page 69 of 76
ol
ided
OL
croport. The
esigned to
lity when dealing with the host processor. There are
modes of bus operation: Intel nonmultiplexed mode (INM),
ited
0x1E: Port Clock Contr
Bit 0 determines whether PCLK is supplied externally by the
user or derived internally in the AD6652. If PCLK is derived
internally from CLK (Bit 0 = 1), it is output through the PCLK
pin as a master clock. For most applications, PCLK is prov
by the user as an input to the AD6652 via the PCLK pin.
Bits 2 and 1 allow the user to divide CLK by an integer value to
generate PCLK (00 = 1, 01 = 2, 10 = 4, 11 = 8).
MICROPORT CONTR
The AD6652 has an 8-bit microprocessor port or mi
interface is a multimode interface that is d
microport
ive flexibi
g
two
and Motorola nonmultiplexed mode (MNM). The mode is
selected based on host processor and which mode is best su
to that processor. The microport has an 8-bit data bus (D[7:0]),
3-bit address bus (A[2:0]), 3 control pin lines (CS, DS, or RD,
R/W or WR), and one status pin (DTACK or RDY). The
onality of the control signals and status line changes
ng
st writing the
ss to Bits 1–0 of the ACR (Access
ress 7). Bits 7:2 may be set to
ove. The CAR is then written
e internal address (the CAR can be
both are written before the
d Register 1 (DR1)
Data Register DR0
Register DR0 must always be
rt is accomplished in the same
ddress is set up the same way as the
rite. A read from Data Register DR0 activates the internal
read; thus, Register DR0 must always be read first to initiate an
internal read followed by DR1and DR2. This provides the
LSBs of the internal read through the microport (D[7:0]).
dditional data registers can be read to read the balance of the
ternal memory.
functi
slightly depending upon the mode that is chosen.
Write Sequenci
Writing to an internal location is achieved by fir
upper two bits of the addre
Control Register, External Add
as indicated ab
select the channel
with the lower eight bits of th
written before the ACR, as long as
internal access). Data Register 2 (DR2) an
use the write to
must be written first, beca
triggers the internal access. Data
the last register written to initiate the internal write.
Read Sequencing
Reading from the micropo
manner. The internal a
w
8
A
in
Read/Write Chaining
The microport of the AD6652 allows for multiple accesses while
CS is held low (CS can be tied permanently low, if the microport
is not shared with additional devices). The user can access
multiple locations by pulsing the WR or RD line and changing
the contents of the external 3-bit address bus. External access to
the external registers of Table 22 is accomplished in one of two
modes using the CS, RD, WR, and MODE inputs. The access
modes are Intel nonmultiplexed mode and Motorola
nonmultiplexed mode. These modes are controlled by the
MODE input (MODE = 0 for INM, MODE = 1 for MNM). CS,
RD, and WR, control the access type for each mode.
ed Mode (INM)
e AD6652 microprocessor
ode. The access type is controlled by the user with the
Intel Nonmultiplex
MODE must be tied low to operate th
in INM m
CS, RD (DS), and WR (R/W) inputs. The RDY (/DTACK) signal
is produced by the microport to communicate to the user that
an access has been completed. RDY (DTACK) goes low at the
start of the access and is released when the internal cycl
complete. See the timing diagrams fo
e is
r both the read and write
rams section.
e AD6652 microproces-
ontrolled by the user
modes in the DDC Timing Diag
Motorola Nonmultiplexed Mode (MNM)
MODE must be tied high to operate th
e access type is c
sor in MNM mode. Th
with the CS, DS (RD), and R/W (WR) inputs. The DTACK
he microport to communicate to
completed. DTACK
(RDY) signal is produced by t
ccess has been
the user that an a
(RDY) goes
omplete and then returns high
low when an internal access is c
after DS (RD) is de-asserted. See the timing diagrams for both
the read and write modes in the DDC Timing Diagrams
section.
Microport Programming Overview
sing scheme. The external
ed to access the
emory
rt memory map. The 4-channel memory
ages are decoded using A[9:8] given in the External Memory
ister 7 of the access control register (ACR). The output port
register memory map is selected using Bit 5 of External
Address 3 (sleep register). When this bit is written with a 0, the
channel memory map is selected; when this bit is 1, the output
port memory map is selected.
The AD6652 uses an indirect addres
memory map (or external registers) is us
internal memory maps that are made up of a channel m
map and an output po
p
Reg
相關(guān)PDF資料
PDF描述
AD7575JP-REEL 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20
AD7575KP-REEL 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20
AD7741YR-REEL7 VOLTAGE-FREQUENCY CONVERTER, 6.144 MHz, PDSO8
AD8402AR1-REEL DUAL 1K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
AD8402ARU100-REEL DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6653 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:IF Diversity Receiver
AD6653-125EBZ 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653
AD6653-150EBZ 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk
AD6653BCPZ-125 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64
AD6653BCPZ-150 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*