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參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 40/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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Preliminary Technical Data
AD6652
Rev. PrC | Page 45 of 76
CHANNEL 0
START
SYNC
L
FRO
CONTROL REGISTER
SOFT SYNC0 EXT ADD 5:0
START SYNC ENABLE, 0x82:0
A
B
SYNC C
88:8
x88:7
, 0x82:1 AN
SYNC A
SYNC C
SYNC D
0x88:8
0x88:7
FTWARE SYNC
SSING CHANNEL
SYNC
SYNC B PIN
SYNC
03198-0-040
annel 0 ; Note t
to Enable
to Be Rou
date hold-off counter
1.
Place the channels in sleep mode (a hard reset to the
AD6652 RESET
CHANNEL 0
HOP
SYNC
HOP EXT ADD 5:5
SOFT SYNC0 EXT ADD 5:0
D EXT ADD 4:5
SELECT LINES
FROM NCO
MULTIPLEXER
TO START HOLD-OFF COUNTER
CONTROL REGISTER
SE ECT LINES
M NCO
MULTIPLEXER
TO NCO HOLD-OFF COUNTER
START EXT ADD 5:4
AND EXT ADD 4:4
SYNC
PIN SYNC_EN A*
SYNC D
PIN SYNC_EN B*
A PIN
0x
0
PIN SYNC_EN C*
HOP SYNC ENABLE
C PIN
SYNC B
PIN SYNC_EN D*
D PIN
AD6652 HARDWARE AND SO
CONTROL FOR ONE PROCE
* FROM EXTERNAL MEMORY ADDRESS REGISTER 4:3-0
NOTE: ALL CIRCUITRY AND SIGNALS ARE IDENTICAL AND REPEATED FOR
EACH CHANNEL EXCEPT SOFT SYNCx. SOFT SYNCx CONTROL SIGNALS
ARE ASSIGNED TO A SINGLE CHANNEL AND ARE NOT SHARED WITH ANY
OTHER CHANNEL.
Figure 44. Synchronizing Signal Routing Example, Ch
either a Pin_Sync or a Soft_Sync Signal
Start with Soft Sync
The AD6652 includes the ability to synchronize channels or
chips using the microport. One action to synchronize is the
start of channels or chips. The start up
hat Multiple Qualifiers Are Required
ted to a Hop or Start Hold-Off Counter
(0x83) in conjunction with the start bit and sync bit (External
Address 5) allows this synchronization. The start update hold-
off counter delays the start of a channel by the 16-bit value
programmed at 0x83 (number of AD6652 CLK periods). Use
the following method to synchronize the start of multiple
channels via microprocessor control:
pin forces all 4 DDC processing channels
up in sleep mode).
2.
Write the start hold-off counter(s) (0x83) to a value from 1
to 216 1. If the chip or channels have not been completely
programmed, write all other registers now.
count of
g as set in
er,
ich
e soft sync command data) to
when the DDC channel begins processing data is equal to the
time period set up by the start hold-off counter value at 0x83 +
6 CLK cycles.
3.
Write the start bit and the applicable channel sync bit(s)
high at External Address 5. This triggers the start hold-off
counters to begin their count. The counters are clocked
with the AD6652 CLK signal. When it reaches a
one, the sleep bits of the selected channels are set low to
turn on the channel with the new or existing operating
parameters.
Note: Each channel has a redundant soft-sync control register at
Address 0x81. This register mimics the programmin
the External Memory Address 5:5–4. You may control the soft-
sync function of a DDC channel by writing to the 0x81 regist
if it is advantageous to do so in your application.
Note that the time from when the DTACK pin goes high (wh
acknowledges the receipt of th
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