參數(shù)資料
型號： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁數(shù)： 30/76頁
文件大?。?/td> 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 36 of 76
t-
e
er stage with 20-bit resolution. The coefficient
oefficients with 20-bit
n. On every CLK cycle,
for I and one tap for Q
e same co
ts. The RCF output
ata and 24
Q data.
RAM COEFFICIENT FILTER
The final signal processing stage is a sum-of-products decima
ing filter with programmable coefficients. A simplified block
diagram is shown in Figure 40. The data memories I-RAM and
Q-RAM store the 160 most recent complex samples from th
previous filt
memory, CMEM, stores up to 256 c
resolutio
one tap
are calculated using th
efficien
consists of 24 bits I d
bits
160
× 20B
I-RAM
I IN
I OUT
256
× 20B
C-RAM
160
× 20B
Q-RAM
Q IN
Q OUT
Σ
03198-0-036
Figure 40. RAM Coefficient Filter Block Diagram
channel to decimate the data rate. The decima-
tion register is an 8-bit register that can decimate from 1 to 256.
he RCF decimation is stored in 0xA0 in the form of MRCF 1.
The input rate to the RCF is fSAMP5.
RCF DECIMATION PHASE
Use the RCF decimation phase to synchronize multiple filters
within a chip. This is useful when using multiple channels
within the AD6652 to implement a polyphase filter, requiring
that the resources of several filters be paralleled. In such an
application, two RCF filters would be processing the same data
from the CIC5. However, each filter is delayed by one-half the
decimation rate, thus creating a 180° phase difference between
the two halves. The AD6652 filter channel uses the value stored
in this register to preload the RCF counter. Therefore, instead of
starting from 0, the counter is loaded with this value, thus
creating an offset in the processing that should be equivalent to
the required processing delay. This data is stored in 0xA1 as an
8-bit number.
RCF FILTER LENGTH
The maximum number of taps this filter can calculate, Ntaps, is
given by the following equation. The value Ntaps 1 is written to
the channel register within the AD6652 at address 0xA2.
RCF DECIMATION REGISTER
Use each RCF
T
∫
×
∫
≤
160
,
min
5
SAMP
RCF
CLK
taps
M
N
where min indicates that Ntaps is the lesser of the two values,
separated by the comma, that appear within the brackets.
and
d
o a 160x40 RAM.
ilter output, it starts by multiplying
the oldest value in the data RAM by the first coefficient, which
is pointed to by the RCF coefficient offset register (0xA3). This
value is accumulated with the products of newer data words
multiplied by the subsequent locations in the coefficient RAM
until the coefficient address RCFOFF + Ntaps 1 is reached.
Table 16. Three-Tap Filter
Coefficient Address
Impulse Response
Data
The RCF coefficients are located in addresses 0x00 to 0x7F
are interpreted as 20-bit twos complement numbers. When
writing the coefficient RAM, the lower addresses are multiplie
by relatively older data from the CIC5, and the higher coeffi-
cient addresses are multiplied by relatively newer data from the
CIC5. The coefficients need not be symmetric, and the
coefficient length, Ntaps, may be even or odd. If the coefficients
are symmetric, then both sides of the impulse response must be
written into the coefficient RAM.
Although the base memory for coefficients is only 128 words
long, the actual length is 256 words long. There are two pages,
each of 128 words long. The page is selected by Bit 8 of 0xA4.
Although this data must be written in pages, the internal core
handles filters that exceed the length of 128 taps. Therefore, the
full length of the data RAM may be used as the filter length
(160 taps).
The RCF stores the data from the CIC5 int
160x20 is assigned to I data and 160x20 is assigned to Q data.
The RCF uses the RAM as a circular buffer, so that it is difficult
to know in which address a particular data element is stored.
When the RCF calculates a f
0
h(0)
N(0) oldest
1
h(1)
N(1)
2 = (Ntaps 1)
h(2)
N(2) newest
The RCF coefficient offset register has two purposes. The main
purpose of this register is for rapid filter changes, by allowing
multiple filters to be loaded into memory and then selected
simply by changing the offset as a pointer. The other use of this
register is to form part of symbol timing adjustment. If the
desired filter length is padded with zeros on the ends, then the
starting point can be adjusted to form slight delays in when the
filter is computed with reference to the high-speed clock. This
allows for vernier adjustment of the symbol timing. Course
adjustments can be made with the RCF decimation phase.
The output rate of this filter is determined by the output rate of
the CIC5 stage and MRCF, as follows:
RCF
SAMP
SAMPR
M
5
∫
=
∫
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