參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 59/76頁(yè)
文件大小： 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 62 of 76
Table 28. Memory Map for Input Port Control Registers
Channel Address
Register
Bit Width
Comments
00
Lower Threshold A
10
9–0:
Lower threshold for Input A
01
Upper Threshold A
10
old for Input A
9–0:
Upper thresh
02
Dwell Time A
20
19–0:
Minimum time below Lower Threshold A
03
Gain Range A Control Register
5
4:
Output polarity LIA and LIA
3:
(0) Reserved
2–0:
Linearization hold-off register
04
Lower Threshold B
10
9–0:
Lower threshold for Input B
05
Upper Threshold B
10
9–0:
Upper threshold for Input B
06
Dwell Time B
20
19–0:
Minimum time below Lower Threshold B
07
Gain Range B Control Register
5
4:
Output polarity LIB and LIB
3:
(0) Reserved
2–0:
Linearization hold-off register
OUTPUT PORT CONTROL REGISTERS
This group of registers is dedicated to data management after
individual channels have processed the incoming data. They
manage data interleaving, 2x interpolation, AGC functions,
output port assignment, and output port setup. Because there
are two output ports, A and B, the data must be funneled from
c
ith
or a
ription of all registers.
register includes
ly
st
and filter, and the AGC
e stage is shut down a
vents any urther propagation of data to t e remaining
tages. This condition is desirable when the t ree stages are not
eeded and ower conservation is desired. W en Bit 3 is high,
e interleav
tage is active and works to int
eave the dat of
p to 4 DDC channels according to the truth table of Bit 2 and
it 1. The da are then propagated to the LH and AGC st
s
bypass
hannels are interleaved. The truth
onfiguration would be 2 times
o channels can be inter-
g only Bit 1; Bit 2 is the LHB B
ut
o
Bit 4 of this register sets the mode of operation for the AGC.
When this bit is 0, the AGC tracks to maintain the output signal
level; when this bit is 1, the AGC tracks to maintain a constant
clipping error. See the Automatic Gain Control section for more
details about these two modes.
configure the synchronization of the AGC.
T
or filter in the AGC can be directly synchro-
n
lly generated signal. When synchronized, the
A
update sample for the AGC error calculation
a
y, the AGC gain changes can be synchro-
Rake receiver.
four channels down to two. These registers are responsible for
guiding the data directly to the proper output port(s) or
detouring the data through other post-filtering stages (AGC,
and so on) before the output port is selected.
To access the output port registers for Output Ports A and B, Bit
5 of External Address 3 (the sleep register) must be written logi
high. The channel address register (CAR) is then written w
the address to the correct output port register. See Table 29 f
complete listing and brief desc
0x00-0x07: Reserved
Reserved. All bits should be written logic low.
0x08: LHB A Control Register
LHB is the acronym for interpolating half-band, with L being a
widely accepted symbol for interpolation. This
the interleaving stage as well as the half-band filter stage, as
shown in Figure 55. These two stages are controlled separate
from the final AGC stage, so that they do not get lost among the
numerous AGC control elements.
Bit 3, the LHB A enable bit, acts as an on/off switch for the
interleave age, half-b
stage. See
Bit 3 is low, the interleav
nd
pre
f
h
s
h
n
p
h
th
e s
erl
a
u
B
ta
B
age
with
opportunities included.
Bits 2 and 1 choose which c
table for these bits is shown in Table 29.
Bit 0, the bypass bit, when high, directs data from the interleave
stage to bypass the half-band filter stage and proceed directly to
the AGC stage without interpolation. The channel data streams
are still interleaved, but they are not filtered or interpolated. The
maximum data rate from this c
the chip rate.
When Bit 0 is low, data from the interleave stage is passed
through the half-band filter and undergoes a 2x interpolation
rate. The maximum output data rate of the half-band is four
times the chip rate.
0x09: LHB B Control Register
Same as LHB A, except that only tw
leaved. Channels are selected usin
enable bit.
0x0A: AGC A Control Register
Bits 7–5 define the output word length of the AGC. The outp
word can be 4 to 8, 10, 12, or 16 bits wide. The truth table t
obtain different output word lengths is given in the Tab
memory map, 0x0A.
Bits 3–1 are used to
he CIC decimat
ized to an externa
GC outputs an
nd filtering. This wa
nized to a
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