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| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 39/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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AD6652
Preliminary Technical Data
Rev. PrC | Page 44 of 76
CHANNEL/CHIP SYNCHRONIZATION
The AD6652 has been designed to easily synchronize two
common functions: Start and Hop. While the AGC stage may
also be synchronized, it is not accommodated using the versatile
soft-sync and pin-sync signals normally associated with
AD6652 synchronization. Start and Hop functions are described
in detail below. The synchronization is accomplished with the
use of a shadow register and a hold-off counter. See Figure 43
for a simplified schematic of the NCO shadow register and
NCO frequency hold-off counter to understand basic operation.
Triggering of the hold-off counter can occur with either a
Soft_Sync (via the microport), or a Pin_Sync (via any of the
four AD6652 SYNC pins A, B, C, and D). Figure 44 details how
synchronization signals are managed for a single receive
processing channel.
REGISTER
READBACK
TC
ENB
NCO “HOP”
HOLD-OFF
COUNTER
Q0
Q31
NCO
SHADOW
REGISTER
D0
D31
Q0
Q31
NCO
FREQUENCY
REGISTER
SOFT SYNC
FROM
0x85 AND
0x86 NCO
FREQUENCY
I0
TO NCO
PHASE
ACCUMULATOR
32
D0
D31
D0
D15
PRE-LOAD
INPUTS FROM
0x84
FROM TC OF
PIN SYNC
CLK
START HOLD-OFF
COUNTER
03198-
0-
039
.
s can be used simultane-
l
STA
Start refers to the startup of an individual channel or chip, or
lt
sleep
(low
Figure 43. NCO Shadow Register and Hold-Off Counter
There are two types of synchronization stimuli to choose from:
Soft_Sync and Pin_Sync. The first method is initiated over the
microport or serial programming port using a software routine
The second method relies on an external stimulus that is
attached to one of the four synchronization input pins (SYNC
A, B, C, and D). In both cases, a logic high triggers the
synchronization process. Both method
ous y by setting the appropriate qualifiers.
RT
mu iple chips. If a channel is not used, it should be placed in
mode to reduce power dissipation. Following a hard reset
pulse on the AD6652 RESET pin), all channels are placed
in sleep mode. Channels may also be manually placed in sleep
mode by writing to the register controlling the sleep function,
External Address 3:3–0.
Before and after a start command is received by one or more
channels, the following occurs:
1.
Just before the Start command is issued, while the channel is
in sleep mode, any or all control registers, including filter
coefficients, may be safely reprogrammed without crashing
the AD6652 or creating unwanted output.
2.
When a Start_Sync pulse is received, it transfers the
contents of the channel’s start hold-off register, 0x83, to the
counter’s preload inputs and commences counting. When
the count reaches a value of one, the channel is awakened
and initialized with the information from each applicable
register for a proper channel startup. However, if the start
preload value is 0, this defeats the start function, and the
channel remains dormant.
Note that Start does not affect the AGC hold-off counter. The
counter can be triggered only by setting the sync now bit or by
pin sync signals (see the Automatic Gain Control section).
What happens if a Start_Sync pulse is received while the
channel is awake (actively processing data)? This can actually be
a very useful tool to dynamically adjust the RCF phase or
timing to allow synchronization of multiple AD6652 ICs. Refer
to the discussions of Registers 0x83 and 0xA1 in the Channel
Address Register (CAR) section for further explanation.
Start with No Sync
iple channels or
multiple AD6652s, use the following method to initialize the
device:
2.
e
ne with the
newly programmed or previous parameters.
If no synchronization is needed to start mult
1.
To program a channel, put it in sleep mode (bit high,
External Address 3:3–0), then load all appropriate control
and memory registers to set up the proper channel
configuration.
Load the start hold-off counter (0x83) with a 16-bit valu
from 1 to 216 1.
3.
Set the channel’s sleep bit low (External Address 3:3–0).
Awakening from sleep involves an internally generated
start command that performs the same functions as a
software-generated sync pulse. This activates the channel
after the hold-off counter reaches a value of o
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