參數(shù)資料
型號： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁數(shù)： 52/76頁
文件大?。?/td> 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 56 of 76
NNEL 1
ORY MAP
20
8
CAR, EXTERNAL
ADDRES
ADDRESS
DATA B
DR2, DR1,
EXTERNAL
ADDRESSES 2, 1, 0
ACCESS TO OUTPUT CONTROL
REGISTERS, BIT 5, SLEEP REGISTER,
EXTERNAL
RE
* CHANNEL DECODER CAN BE
OVERRIDDEN BY BROADCAST FEATURE.
A[9:8] FROM
0x08
0x00
S
S1
D1
ADDRESS 7
S2
4
ENB
D
2
CHANNEL
DECODER*
CHA
MEM
ACR,
EXTERNAL
CHANNEL 0
MEMORY MAP
CHANNEL 3
MEMORY MAP
CHANNEL 2
MEMORY MAP
OUTPUT PORT
CONTROL
REGISTERS
ENB
S 6
BUS
US
DR0,
ADD
SS 3
BITS [1:0] OF
0x1E
INPUT PORT
CONTROL
REGISTER
03198-0-050
ock Diagram of the A
52 Internal Mem
nd Controls
SYNC Register
his register is used to
itiate software-generated SYNC events
ugh the microport
the programming of Bits 4
5 at External Addr
written high, then
hop hold-off coun
aded and begins
unt down. When t
aches a value of one, the
el’s NCO frequen
ulator is loaded with the data
hannel Address
hen the start bit is
ten high, the start
aded with the value
ddress 0x83 and b
en the count
hes a value of one,
x80 is written
and the channel is
SYNC Register
egister mimics B
5, and 6 of External Memory Map
ddress 4. Since the pr gramming at External Memory Address
pplies to all four ch
ls, you may customize a particular
nnel by overwritin
he data in 0x82.If you are satisfied with
e initial programmin provided by External Address 4, you do
ot need to reprogram he elements of this register.
nlike the two bits in 0x81 above, setting the Hop_En or the
t_En (Bits 1 and 0) o
gger anything.
se bits simply allow
nchronizing
al to be routed to t
op multi-
ers. Even though a
ach the
iplexer, it still nee
accomplished
y Bits 8 and 7 of 0x88,
cussed below. The schematic
agram of Figure 44 is helpful in understanding the Pin_SYNC
ling and selection
ers.
it 2 of 0x82 engages t
irst Sync Only function for the
channel. This bit is a copy of External Address 4, Bit 6, but may
be overw
n to
articular
channel
s bi
YNC restarts or rehops
the chan
thi
he first sync pulse causes
the actio
0x83: Start Ho
The star
the 16-bit value
written t this address. When the Start function is triggered by
either a
C or Pin_SYNC, the hold-off counter begins
decrem
g. When the count reaches a value of one, the
channel
br
t out of sleep mode and begins processing
data. If t
is already running, the phase of the filter(s) is
adjusted
that
can be synchronized.
A perio
pulse o
is way to
adjust th
ming
lution of the ADC
sample
See
ion for further
informa
abou
ent. If this register is
written
gic 1
ccurs immediately after the
SYNC p lse arriv
, then the counter
does no espond
0x84: Hop or Fr
ff Counter
The NC
cy hold-off counter is loaded with the 16-bit
value wr
his address upon receipt of either a Soft_SYNC
or Pin_S
h
count re
es a va
-bit NCO frequency word is
updated
he
d 0x86. This is known as a
hop or H
_SYN
ister to a value of 1 causes
the NCO
quen
en the SYNC
comes i
he ch
no Hop
occurs. N O hops ca
tinuous or non-
phase-continuous,
ate of Bit 3 of the
Figure 54. Bl
D66
ory Maps a
0x81: Soft_
T
in
thro
. It mimics
and
ess 5. If the hop bit is
ss 0x84 is lo
the
ter at Addre
e
to co
he count r
chann
from C
cy accum
es 0x85 and 0x86. W
hold-off counter is lo
writ
at A
egins to count down. Wh
reac
the sleep bit in Address 0
low
started.
0x82: Pin_
This r
its 4,
A
o
4 a
anne
cha
g t
th
g
n
t
U
Star
The
f this register does not tri
, or enable, an external sy
sign
he channel’s Start and/or H
plex
signal has been enabled to re
mult
ds to be selected. This job is
b
as dis
di
enab
bits of the involved regist
B
he F
ritte
change the programming of a p
. If thi
t is clear, each PIN_S
nel. If
s bit is set, then only t
n to occur.
ld-Off Counter
t hold-off counter is loaded with
o
Soft_SYN
entin
is
ough
annel
he ch
such
multiple AD6652s
dic
n the SYNC pin can be used in th
e ti
of the filters with the reso
clock.
the 0xA1 register descript
tion
t filter phase adjustm
to Lo
, then the start o
u
es. If it is written to Logic 0
t r
to a SYNC pulse.
equency Hold-O
O frequen
itten to t
YNC. T e counter begins counting, and when the
ach
lue of one, the 32
with t
values at 0x85 an
op
C. Writing this reg
fre
cy to be updated immediately wh
ten to a 0, then
nto t
C
annel. If it is writ
n be either phase-con
depending upon the st
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