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參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 55/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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Preliminary Technical Data
AD6652
Rev. PrC | Page 59 of 76
.
0x92: rCIC2 Scale
The rCIC2 scale register is used to provide attenuation to
compensate for the gain of the rCIC2 and to adjust the
linearization of the data from the floating-point input. The use
of this scale register is influenced by the rCIC2 growth. For
more details, see the Second-Order rCIC Filter section.
Bit 11 is reserved. Write all bits to Logic 0.
Bit 10 is reserved. Write all bits to Logic 0.
Bits 9–5 are the actual scale value used when the level indicator,
LI pin associated with this channel, is active (Logic 1).
Bits 4–0 are the actual scale value used when the level indicator,
LI pin associated with this channel, is inactive (Logic 0).
0x93: Reserved
Eight bits, reserved (must be written low).
0x94: CIC5 Decimation – 1 (MCIC51)
This register is used to set the decimation in the CIC5 filter. The
8-bit value written to this register is the decimation minus one.
0x95: CIC5 Scale
The 5-bit CIC5 scale factor is used to compensate for the
growth of the CIC5 filter. See the Fifth-Order CIC Filter section
for details.
0x96: Reserved
Reserved (must be written low).
0x97-0x9F: Unused
Unused.
0xA0: RCF Decimation 1 (MRCF 1)
Sets the decimation of the RCF stage. The value written to this
register is the desired decimation minus one. Although this is an
8-bit register that allows decimation up to 256, most filter
designs should be limited to between 1 and 32. Higher decima-
tions are allowed, but the alias rejection of the RCF may not be
acceptable for some applications.
0xA1: RCF Decimation Phase (PRCF)
This register allows any one of the MRCF phases of the filter to be
used and can be adjusted dynamically. Each time a filter is
started, then this phase is updated. When a channel is synchro-
ing chosen here. This can be used
r or
o
ord
mory is used for a filter. It can be used to select
to memory and
egister that controls the
data to
ta
l
9 is set.
ce of the input data to the
r to
MrCIC2 must be chosen larger than LrCIC2, and both must be
chosen such that a suitable rCIC2 scalar can be chosen. For
more details, see the Second-Order rCIC Filter section.
0x91: rCIC2 Interpolation 1 (LrCIC2 1)
This register is used to set the interpolation in the rCIC2 filter
The value written to this register is the interpolation minus one
The rCIC2 interpolation can range from 1 to 512, depending
upon the decimation of the rCIC2. There is no timing error
associated with this interpolation. For more details, see the
Second-Order rCIC Filter section.
nized, it retains the phase sett
as part of a timing recovery loop with an external processo
can allow multiple RCFs to work together while using a single
RCF pair. See the RAM Coefficient Filter section for further
details.
0xA2: RCF Number of Taps Minus One (NRCF 1)
The number of taps for the RCF filter minus one is written t
this register.
0xA3: RCF Coefficient Offset (CORCF)
This register is used to specify which section of the 256-w
coefficient me
among multiple filters that are loaded in
referenced by this pointer. This register is shadowed, and the
filter pointer is updated (from the shadow register) on every new
filter output sample. This allows the coefficient offset to be
written without disturbing operation, even while a filter is being
computed. The next sample that comes out of the RCF is with
the new filter.
0xA4: RCF Control Register
The RCF control register is an 11-bit r
general features of the RCF as well as output formatting. The
bits of this register and their functions are described below.
Bit 10 bypasses the RCF filter and sends the CIC5 output
the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5 da
can be accessed from this register, if Bit 9 of the output contro
register at Channel Address 0xA
Bit 9 of this register controls the sour
RCF. If this bit is 0, then the RCF processes the output data of its
own channel. If this bit is 1, then it processes the data from the
CIC5 of another channel. The CIC5 channels that the RCF can
be connected to when this bit is 1 are shown in the Table 26.
These can be used to allow multiple RCFs to be used togethe
process wider bandwidth channels.
Table 26. RCF Input Configurations
Channel
RCF Input Source when Bit 9 Is 1
0
1
0
2
1
3
1
Bit 8 is used as an extra address to allow a second block o
128 words of CMEM to be addressed by the channel addr
at 0x00–0x7F. If
f
esses
this bit is 0, then the first 128 words are written;
if this bit is 1, then the next 128 words are written. This bit is
used to program only the coefficient memory so that filters
longer than 128 taps can be realized.
Bit 7 is used to control the output formatting of the AD6652’s
RCF data. This bit is used only when the 8 + 4 or 12 + 4
floating-point modes are chosen. These modes are enabled by
Bits 5 and 4 of this register. When this bit is 0, then the I and Q
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