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參數(shù)資料
| 型號(hào)： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 44/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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Preliminary Technical Data
AD6652
Rev. PrC | Page 49 of 76
PCLKn
PxREQ
PxACK
Px[15:0]
tDPP
I[15:0]
Q[15:0]
PxIQ
PxCH[1:0]
PxCH[1:0] =
Channel #
tDPCH
tDPIQ
t
DPREQ
03198-
0-
042
Figure 46. Channel Mode Interleaved Format
ast
nificant byte. The PAIQ and PBIQ output indicator pins are
h during the PCLK cycle. Note that if data from multiple
channels is output consecutively, the PAIQ and PBIQ output
indicator pins remain high until data from all channels has been
output.
The 8-bit concurrent format provides 8 bits of I data and 8 bits
of Q data simultaneously during one PCLK cycle, also triggered
on the rising edge of PCLK. The I byte occupies the most
significant byte of the port, while the Q byte occupies the le
sig
set hig
PxCH[1:0]
PCLKn
tDPREQ
PxREQ
PxACK
tDPP
Px[15:0]
I[15:8]
Q[7:0]
PxIQ
tDPIQ
PxCH[1:0] =
Channel #
tDPCH
03198-0-043
Figure 47. Channel Mode 8I/8Q Parallel Format
The PACH[1:0] and PBCH[1:0] pins provide a 2-bit binary
value indicating the source channel of the data currently being
output.
Care should be taken to read data from the port as soon as
possible. If not, the sample will be overwritten when the next
new data sample arrives. This occurs on a per-channel basis;
that is, a Channel 0 sample is overwritten only by a new
Channel 0 sample, and so on.
The order of data output is dependent on when data arrived at
the port, which is a function of total decimation rate, start hold-
off values, and so on. Priority order is, from highest to lowest,
Channels 0, 1, 2, and 3.
AGC A accepts data from
hannel 3, while AGC B accepts data from
nfigured such that the generation of output samples from
e (by typically 180°). Each parallel
either one or both AGCs. Bit 1 and
.
o
re asserted, the next rising edge of PCLK triggers the
C I word for one PCLK cycle. The PAIQ
cator pins are high during this cycle, and
g the
CLK cycle. If the AGC gain word has been updated
since the last sample, a 12-bit RSSI word is provided during the
PCLK cycle following the Q word of 12 MSBs of the parallel
port data pins. This RSSI word is the bit-inverse of the signal
gain word used in the gain multiplier of the AGC.
The data provided by the PACH[1:0] and PBCH[1:0] pins in
AGC mode is different than that provided in channel mode. In
AGC mode, PACH[0] and PBCH[0] indicate the AGC source of
the data currently being output (0 = AGC A, 1 = AGC B).
PACH[1] and PBCH[1] indicate whether the current data is an
I/Q word or an AGC RSSI word (0 = I/Q word, 1 = AGC RSSI
word). The two different AGC outputs are shown in Figure 48
and Figure 49.
AGC MODE
Parallel port channel mode is selected by clearing Bit 0 of
Addresses 0x1A and 0x1C for Parallel Ports A and B, respec-
tively. I and Q data output in AGC mode are output from the
AGC, not the individual channels.
Channel 0 to C
Channel 2 and Channel 3. Each pair of channels is required to
be co
the channels is out of phas
port can provide data from
Bit 2 of Register Addresses 0x1A (Port A) and 0x1C (Port B)
control the inclusion of data from AGCs A and B, respectively
AGC mode provides only one I&Q format, which is similar t
the 16-bit interleaved format of channel mode. When both REQ
and ACK a
output of a 16-bit AG
and PBIQ output indi
are low otherwise. A 16-bit AGC Q word is provided durin
subsequent P
PCLKn
PxREQ
PxACK
Px[15:0]
PxIQ
PxCH[1:0]
tDPREQ
tDPP
I[15:0]
Q[15:0]
tDPIQ
PxCH[0] = AGC #
PxCH[1] = 0
tDPCH
03198-0-044
Figure 48. AGC with No RSSI Word
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