參數(shù)資料
型號： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網絡
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁數(shù)： 54/76頁
文件大?。?/td> 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 58 of 76
Bit Wid
omm
Channel Address
Register
th
C
ents
A4
RCF Control Register
11
10:
RCF bypass BIST
9:
own 0, other 1)
RCF input select (
8:
ank 1/0
Program RAM b
7:
n exponent
Use commo
6:
Force output scale
5-4:
Output format
1x: Floating point 12 + 4
01: Floating point 8 + 4
00: Fixed point
3-0:
Output scale
A5
BIST Signature for I Path
16
BIST-I
A6
BIST Signature f r Q Path
o
16
BIST-Q
A7
BIST Outputs to Accumulate
20
)
19-0:
Number of outputs (counter value read
A8
RAM BIST Control Register
3
2:
D-RAM fail/pass
1:
C-RAM fail/pass
0:
RAM BIST enable
A9
Output Control Register
9:
Map RCF data to BIST registers
5:
Output format
1: 16-bit I and 16-bit Q
0: 12-bit I and 12-bit Q
4-0:
Reserved, write to Logic 0
0x87: NCO Phase Offset Register
This register represents a 16-bit phase offset to the NCO. It can
be interpreted as values ranging from 0 to just under 2π. The
16-bit phase offset is added to the 16 MSBs of the 32-bit NCO
phase accumulator to arrive at the final phase angle number
used to compute the amplitude value.
0x88: NCO Control Register
This 9-bit register controls features of the NCO and the
channel. The bits are defined below. For more detail, see the
hich one of the four
Selected
Bits 8–7 of this register choose w
Pin_SYNC pins (A, B, C, or D) is used by the channel to initiate
channel start and frequency hop functions. These bits can also
be used to make timing adjustments to a channel.
Table 25 shows the bit logic state needed to select a particular
Pin_Sync.
Table 25. Bit Logic States for Sync Pins
0x88:8
0x88:7
Sync Pin
0
A
0
1
B
1
0
C
1
D
Bit 6 of this register defines which ADC channel, A or B, is us
by the DDC channel being programmed. If this bit is low, then
Input Port A selected; if this bit is hig
ed
h, Input Port B is selected.
n logic low.
n this bit is set to 0, the
.
pri-
es is
for more information on the use
ction.
f this regi
tage
e bypassed.
rt A is
ed down th
nel and the data from Input
1 (MrCIC2 1)
This register sets the decimation in the rCIC2 filter. The value
the interpolation.
Bits 5–4 are reserved and must be writte
Bit 3 determines whether or not the phase accumulator of the
NCO is cleared when a hop occurs. The hop can originate from
either Pin_SYNC or Soft_SYNC. Whe
hop is phase-continuous and the accumulator is not cleared
When this bit is set to 1, the accumulator is cleared to 0 before it
begins accumulating the new frequency word. This is appro
ate when multiple channels are hopping from different
frequencies to a common frequency.
Bits 2–1 control whether or not the phase and amplitude dither
functions of the NCO are activated. The use of these featur
determined by the system constraints. See the Numerically
of dither. As usual, a logic high activates the fun
Bit 0 o
ster allows the NCO frequency translation s
to b
When this occurs, the data from Input Po
pass
e I path of the chan
Port B is passed down the Q path of the channel. This allows a
real filter to be performed on baseband I and Q data.
Ox89-0x8F: Unused
Unused.
0x90: rCIC2 Decimation
written to this register is the decimation minus one. The rCIC2
decimation can range from 1 to 4096, depending upon the
interpolation of the channel. The decimation must always be
greater than
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