- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298813 > AD6652XBC (ANALOG DEVICES INC) SPECIALTY TELECOM CIRCUIT, PBGA256 PDF資料下載
參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 50/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD6652
Preliminary Technical Data
Rev. PrC | Page 54 of 76
ics such as
e broadcast bit, which determines how
hips.
adcast bit is high, the Instruction[3:0] word allows
Bit 6
readback is not valid because of the potential for
e
ignored. If the
he
ssed.
7:5–2
nt
ACCESS CONTROL REGISTER (ACR)
External Address 7
The ACR specifies certain programming characterist
autoincrement or broadcast, which are to be applied to the
incoming instructions, and selects which channel(s) are to be
programmed by the microport or serial port.
Bit 7 of this register is the autoincrement bit. If this bit is a 1,
then the CAR register, described in the Channel Address
Register (CAR) section, increments its value after every access
to the channel. This allows blocks of address space such as
coefficient memory to be initialized more efficiently.
Bit 6 of the register is th
Bits 5–2 are interpreted. If broadcast is 0 then Bits 5–2, which
are referred to as instruction bits (Instruction[3:0]), are
compared with the CHIP_ID[3:0] pins. The instruction that
matches the CHIP_ID[3:0] pins determines the access. This
allows up to 16 chips to be connected to the same port and
memory mapped without external logic. This also allows the
same serial port of a host processor to configure up to 16 c
If the bro
multiple AD6652 channels and/or chips to be configured
simultaneously independent of the CHIP_ID[3:0] pins. The
10 possible instructions are defined in Table 23. This is useful
for smart antenna systems, where multiple channels listening to
a single antenna or carrier can be configured simultaneously.
The x’s in the comment portion of the table represent “don’t
cares” in the digital decoding. When broadcast is enabled (
set high)
internal bus contention. Therefore, if readback is subsequently
desired, the broadcast bit should be set low.
Bits 1–0 of the ACR are address bits that decode which of the
four channels are being accessed. If the instruction bits decod
an access to multiple channels, then these bits are
instruction decodes an access to a subset of chips, then t
A[9:8] bits otherwise determine the channel being acce
Table 23. Microport Instructions,
Instruction
Comme
0000
All chips and all channels get the access.
0001
Channels 0, 1, 2 of all chips get the access.
0010
Channels 1, 2, 3 of all chips get the access.
0100
All chips get the access.1
1000
All chips with Chip_ID[3:0] = xxx0 get the access.1
1001
All chips with Chip_ID[3:0] = xxx1 get the access.1
1100
All chips with Chip_ID[3:0] = xx00 get the access.1
1101
All chips with Chip_ID[3:0] = xx01 get the access.1
1110
All chips with Chip_ID[3:0] = xx10 get the access.1
1111
All chips with Chip_ID[3:0] = xx11 get the access.1
1 A[9:8] bits control which channel is decoded for access.
R
t high.
l register is write only. The register
s
bits
e
such
e synchronizing pulse. Writing this bit
he start
g to
ation section
rograms
to
ured. If
o-digital converters) are
rding to the users choice—
IST
Bit 7 is logic low, a negative full-scale signal is generated and
ade available to the internal data bus. If this bit is high, then
e internal pseudorandom noise generator is enabled and this
data is available to the internal input data bus. The combined
functions of Bits 6 and 7 facilitate BIST functions. Also, in
conjunction with the MISR registers, this allows for detailed
in-system chip testing.
CHANNEL ADDRESS REGISTER (CAR)
External Address 6
This is where to write the 8-bit internal address of a channel
register to be programmed. If the autoincrement bit of the AC
is 1, then this value is incremented after every access to the
DR0 register, which in turn accesses the location pointed to by
this address. The channel address register cannot be read back
while the broadcast bit is se
SOFT_SYNC CONTROL REGISTER
External Address 5
The SOFT_SYNC contro
name is somewhat deceiving in that this register also contain
BIST (built-in self-test) commands that turn internal test
signals off or on, namely, pseudonoise and negative full-scale
sine wave, at Bits 7 and 6, explained below.
Bits 0–3 of this register are the SOFT_SYNC channel enable
for each of the four DDC channels. Writing a logic high to on
or all of these bits simply selects the indicated channel(s) to b
recipients of a soft_sync synchronizing pulse—whenever
signal is generated by Bits 4 and 5 of this register as described
below. A pin-sync signal may be used in addition to a soft-sync
signal, if desired.
Bit 4 is the Start softwar
to logic high initiates a one-shot-type pulse to trigger t
hold-off counter of the selected DDC channels accordin
Bits 3–0 above. See the Channel/Chip Synchroniz
also p
for further information. Programming this bit
Channel Address Register 0x82 of each channel.
Bit 5 is the Hop software synchronizing pulse. Writing this bit
logic high initiates a one-shot-type pulse to trigger the hop
frequency hold-off counter of the selected DDC channels
according to Bits 3–0 above. See the Channel/Chip
Synchronization section. Programming this bit also programs
the Channel Address Register 0x82 of each channel.
Bit 6 configures how the internal input data bus is config
this bit is low, then the ADCs (analog–t
connected to the DDC NCOs acco
this is normal operation. If this bit is logic high, then the
internal test signals are connected to all DDC NCOs for B
purposes and this overrides any NCO programmed input
choice. The internal test signals are configured in Bit 7 of this
register.
If
m
th
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7575JP-REEL | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20 |
| AD7575KP-REEL | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20 |
| AD7741YR-REEL7 | VOLTAGE-FREQUENCY CONVERTER, 6.144 MHz, PDSO8 |
| AD8402AR1-REEL | DUAL 1K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14 |
| AD8402ARU100-REEL | DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6653-125EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653 |
| AD6653-150EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk |
| AD6653BCPZ-125 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。