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參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 24/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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AD6652
Preliminary Technical Data
Rev. PrC | Page 30 of 76
set and must fall
igure 38. When the
input signal goes above the upper threshold, the appropriate LI
signal becomes active. Once the si
al falls below the lower
threshold, the counter begins counting. If the input condition
ve the lower threshold, the counter is reset and starts
shown in the figure. Once the counter has terminated
external circuit. The LI line stays active until the input
condition falls below the lower programmed threshold.
To provide hysteresis, a dwell time register (see Table 28) is
available to hold off switching of the control line for a
predetermined number of clocks. Once the input condition is
below the lower threshold, the programmable counter begins
counting high speed clocks. As long as the input signal stays
below the lower threshold for the number of high speed clock
cycles programmed, the attenuator is removed on the terminal
count. However, if the input condition goes above the lower
threshold with the counter running, it is re
below the lower threshold again to initiate the process. This
prevents unnecessary switching between states.
Threshold settings for LI are illustrated in F
gn
goes abo
again, as
to 0, the LI line goes inactive.
HIGH
MANTISSA
LOWER
THRESHO
DWELL TIME
UPPER
THRESHOLD
LD
LOW
COUNTER
RESTARTS
TIME
03198-0-034
Figure 38. Threshold Settings for LI
The LI line can be used for a variety of functions. It can be used
to set the controls of an attenuator, DVGA, or integrated and
used with an analog VGA. To simplify the use of this feature, the
AD6652 includes two separate gain settings, one when this line
red
ld-off is included to compensate for the
ADC and the switching time of the gain
e same value. These 5-bit scale values are
(0x92) and the scaling is
ed to different set points. Note that the input gain
any
pipeline delay that can be
sate for the inherent 7-clock pipeline delay
is inactive (rCIC2_QUIET[4:0] stored in Bits 9:5 of 0x92
register) and the other when active (rCIC2_LOUD[4:0] sto
in Bits 4:0 of 0x92 register). This allows the digital gain to be
adjusted to the external changes. In conjunction with the gain
setting, a variable ho
pipeline delay of the
control element. Together, these two features provide seamless
gain switching.
rCIC2_LOUD[4:0] and rCIC2_QUIET[4:0]
These 5-bit registers contain scale values to compensate for the
rCIC2 gain and external attenuator gain (if used). If no external
attenuator is used, both the rCIC2_QUIET and rCIC2_LOUD
registers contain th
stored in the rCIC2 scale register
applied before the data enters the rCIC2 resampling filter.
Both DDC input ports of the AD6652 have independent gain
control circuits, allowing each respective LI pin to be
programm
control circuits are wideband and are implemented prior to
filtering elements to minimize loop delays. Any of the four
DDC processing channels can be set to monitor either of the
DDC input ports.
The chip also provides appropriate scaling of the internal data,
based on the attenuation associated with the LI signal. In this
manner, data to the DSP maintains a correct scale value
throughout the process, making it totally independent. The
AD6652 includes a programmable
used to compen
associated with the front-end ADC. This feature promotes
smoother switching among gain settings.
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