參數(shù)資料
型號: AD6652XBC
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 17 X 17 MM, MINI, BGA-256
文件頁數(shù): 65/76頁
文件大小: 1802K
代理商: AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 68 of 76
tput on Link Port A. When
Bit 1 has two different meanings, depending on whether data is
two and four
ates that Link Port A
ately from Channels 0 and 1.
be
ta
ds are only
e IQ words are four bytes long, the RSSI
.
n on the limitations and relationship of
Port section.
k
or
data is output on Parallel Port B. When
Bit 0 = 0, Parallel Port B outputs data from the RCF according
to the format specified by Bits 1–4. When Bit 0 = 1, Parallel
Port B outputs the data from the AGCs according to the format
specified by Bits 1 and 2.
In AGC mode, Bit 0 = 1 and Bit 1 determines if Parallel Port B is
able to output data from AGC A. Bit 2 determines if Parallel
Port B is able to output data from AGC B. The order of output
depends on the rate of triggers from each AGC, which in turn is
determined by the decimation rate of the channels feeding it. In
channel mode, Bit 0 = 0 and Bits 1–4 determine which
rocessing channels is output. The
a-
r Q data.
and
e format
ng
a
ode. In this mode, when Bit 1 = 1, Link Port B outputs
de, gain words must be
Bits 6–3 specify the programmable delay value for Link Port B
between the time the link port receives a data ready from the
receiver and the time it transmits the first data word. The link
port must wait at least 6 cycles of the receiver’s clock, so this
value allows the user to use clocks of differing frequency and
phase for the AD6652 link port and the TigerSHARC link port.
For more information on the limitations and relationship of
these clocks, see the Link Port section.
Bit 0 selects which data is ou
Bit 0 = 0, Link Port A outputs data from the RCF according to
the format specified by Bit 1. When Bit 0 = 1, Link Port A
outputs the data from the AGCs according to the format
specified by Bits 1 and 2.
coming from the AGCs or from the RCFs. When data is coming
from the RCFs (Bit 0 = 0), Bit 1 selects between
channel data mode. Bit 1 = 1 indic
transmits RCF IQ words altern
When Bit 1 = 1, Link Port A outputs RCF IQ words from each
of the four channels in succession: 0, 1, 2, 3. However, when
AGC data is selected (Bit 0 = 1), Bit 1 selects the AGC data
output mode. In this mode, when Bit 1 = 1, Link Port A outputs
AGC A IQ and gain words. With this mode, gain words must
included by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, then
AGC A and AGC B are alternately output on Link Port A and
the inclusion or exclusion of the gain words is determined by
Bit 2.
Bit 2 determines if RSSI words are included or not in the da
output. If Bit 1 = 1, Bit 2 = 0. Because the RSSI wor
two bytes long and th
words are padded with zeros to give a full 16-byte TigerSHARC
quad-word. If AGC output is not selected (Bit 0 = 0), then this
bit can be any value.
Bits 6–3 specify the programmable delay value for Link Port A
between the time the link port receives a data ready from the
receiver and the time it transmits the first data word. The link
port must wait at least 6 cycles of the receiver’s clock, so this
value allows the user to use clocks of differing frequency and
phase for the AD6652 link port and the TigerSHARC link port
For more informatio
these clocks, see the Link
0x1C: Parallel Port Control B
Data is output through either a parallel port interface or a lin
port interface. When 0x1D, Bit 7 = 0, the use of Link Port B is
disabled and the use of Parallel Port B is enabled. The parallel
port provides different data modes for interfacing with DSPs
FPGAs.
Bit 0 selects which
combination of the four p
output order depends on the rate of triggers received from each
channel, which is determined by the decimation rate of each
channel. The channel output indicator pins can be used to
determine which data came from which channel.
Bit 5 determines the format of the output data words. When
Bit 5 = 0, Parallel Port B outputs 16-bit words on its 16-bit bus.
This means that I and Q data are interleaved and the IQ indic
tor pin determines whether data on the port is I data o
When Bit 5 = 1, Parallel Port B is outputting an 8-bit I word
an 8-bit Q word at the same time, and the IQ indicator pins are
high.
0x1D: Link Port Control B
Data is output through either a parallel port interface or a link
port interface. The link port provides an efficient data link
between the AD6652 and a TigerSHARC DSP and can be
enabled by setting 0x1D, Bit 7 = 1.
Bit 0 selects which data is output on Link Port B. When
Bit 0 = 0, Link Port B outputs data from the RCF according to
the format specified by Bit 1. When Bit 0 = 1, Link Port B
outputs the data from the AGCs according to th
specified by Bits 1 and 2.
Bit 1 has two different meanings that depend on whether data is
coming from the AGCs or from the RCFs. When data is comi
from the RCFs (Bit 0 = 0), Bit 1 selects between two and four
channel data mode. Bit 1 = 1 indicates that Link Port A
transmits RCF IQ words alternately from Channels 0 and 1.
When Bit 1 = 1, Link Port B outputs RCF IQ words from each
of the four channels in succession: 0, 1, 2, 3. However, when
AGC data is selected (Bit 0 = 1), Bit 1 selects the AGC dat
output m
AGC B IQ and gain words. With this mo
included by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, then
AGC A and B are alternately output on Link Port B and the
inclusion or exclusion of the gain words is determined by Bit 2.
Bit 2 determines whether gain words are included in the data
output. If Bit 1 = 1, Bit 2 = 0. Since the gain words are only two
bytes long and the IQ words are four bytes long, the gain words
are padded with zeros to give a full 16-byte TigerSHARC quad-
word. If AGC output is not selected (Bit 0 = 0), then this bit can
be any value.
相關(guān)PDF資料
PDF描述
AD7575JP-REEL 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20
AD7575KP-REEL 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20
AD7741YR-REEL7 VOLTAGE-FREQUENCY CONVERTER, 6.144 MHz, PDSO8
AD8402AR1-REEL DUAL 1K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
AD8402ARU100-REEL DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6653 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver
AD6653-125EBZ 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653
AD6653-150EBZ 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk
AD6653BCPZ-125 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64
AD6653BCPZ-150 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64