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參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 49/76頁 |
| 文件大小： | 1802K |
| 代理商： | AD6652XBC |
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Preliminary Technical Data
AD6652
Rev. PrC | Page 53 of 76
l accesses to the
EXTERNAL MEMORY MAP
The external memory map is the only way to gain access to the
four channel address register pages and the output port control
register page. This set of eight registers is shown in Table 22.
These registers are collectively referred to as the external
memory map registers, because they control al
channel address space as well as output control registers.
Table 22. External Memory Map
Address
Name
The use of each of these individual registers is described in
detail. It should be noted that the serial control interface has the
same memory map as the microport interface and can carry out
exactly the same functions, although at a slower rate.
Comment
7
Access Control Register (ACR)
7:
Auto increment
6:
Broadcast
5–2:
Instruction[3:0]
1–0:
A[9:8]
6
Channel Address Registers (CAR)
7–0:
A[7:0]
5
SOFT_SYNC Control Register (Write Only)
7:
PN_EN
6:
Test_MUX_Select
5:
Hop
4:
Start
3:
SYNC CH3
2:
SYNC CH2
1:
SYNC CH1
0:
SYNC CH0
4
PIN_SYNC Control Register (Write Only)
7:
Reserved write to logic low
6:
First SYNC only
5:
Hop_En
4:
Start_En
3:
PIN SYNC_EN D
2:
PIN SYNC_EN C
1:
PIN SYNC_EN B
0:
PIN SYNC_EN A
3
SLEEP (Write Only)
7–6:
Reserved write to logic low
5:
Access output port control registers
4:
Reserved low
3:
SLEEP CH3
2:
SLEEP CH2
1:
SLEEP CH1
0:
SLEEP CH 0
2
Data Register 2 (DR2)
7–4:
Reserved
3–0:
D[19:16]
1
Data Register 1 (DR1)
15–8:
D[15:8]
0
Data Register 0 (DR0)
7–0:
D[7:0]
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