參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁數(shù)： 5/76頁
文件大小： 1802K
代理商： AD6652XBC
Preliminary Technical Data
AD6652
Rev. PrC | Page 13 of 76
Pin No.
Mnemonic
Type
Function
P8
LIB
Output
Level Indicator, Input B, Data B.
B3
PACH0_LACLKOUT2
Output
Channel ID Output Bit, LSB, for Parallel Port A, or Link Port A Clock Output.
Function depends on logic state of 0x1B:7 of output port control register.
R2
Output
Channel ID Output Bit, LSB, for Parallel Port B, or Link Port B Clock Output.
Function depends on logic state of 0x1D:7 of output port control register.
F1, D1, D2,
C2, B2, E2,
A4, A2
PA[7:0]_LA[7:0]
Output
Link Port A Data or Parallel Port A Data [7:0], Eight Pins.
P2, R3, N3,
M2, M3, T3,
L1, L2
PB[7:0_LB[7:0]
Output
Link Port B Data or Parallel Port B Data [7:0], Eight Pins.
E1, C1, F3,
G2, G1, G3,
H3, H2
PA[15:8]
Output
Parallel Port A Data [15:8], Eight Pins.
P3, R4, P4,
T4, R5, T5,
P5, R6
PB[15:8]
Output
Parallel Port B Data [15:8], Eight Pins.
N1
PAIQ
Output
Parallel Port A I or Q Data Indicator, I = High, Q = Low.
R1
PBIQ
Output
Parallel Port B I or Q Data Indicator, I = High, Q = Low.
PARALLEL OUTPUT PORT CONTROL
K2
PAACK
Input
Parallel Port A Acknowledge.
H1
PAREQ
Output
Parallel Port A Request.
P7
PBACK
Input
Parallel Port B Acknowledge.
T6
PBREQ
Output
Parallel Port B Request.
MICROPORT CONTROL
C5, A5, C6,
A6, B7, C7,
B8, C8
D[7:0]
I/O
Bidirectional Microport Data, Eight Pins. This bus is three-stated when CS is high.
B4, C3, A3
A[2:0]
Input
Microport Address Bus, 3 Pins.
C4
DS(RD)4
Input
Function depends upon MODE pin.
Active Low Data Strobe when MODE = 1.
Active Low Read Strobe when MODE = 0.
C9
DTACK(RDY)4, 5
Output
Function depends upon MODE pin.
Active Low Data Acknowledge when MODE = 1.
Microport Status Pin when MODE = 0.
B6
R/W (WR)4
Input
Read/Write strobe when MODE = 1. Active Low Write strobe when MODE = 0.
A9
MODE4
Input
Mode Select Pin. 0 = INTEL mode, 1 = Motorola mode.
A7
CS3
Input
Active Low Chip Select. Logic 1 three-states the microport data bus.
1 PDWN pins must be the same logic level: both logic high or both logic low.
2 PACH0 and PACH1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0, 1, 2, or 3) whose data appears on Port A parallel
outputs. Likewise, PBCH0 and PBCH1 identify the channel for Port B.
3 Pins with a pull-down resistor of nominal 70 k.
4 Mode 0 is Intel nonmultiplexed (IMN), and Mode 1 is Motorola nonmultiplexed (MNM). Pin logic level corresponds to mode.
5 Pins with a pull-up resistor of nominal 70 k.
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