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參數(shù)資料
| 型號(hào)： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 48/76頁 |
| 文件大小： | 1802K |
| 代理商： | AD6652XBC |
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AD6652
Preliminary Technical Data
Rev. PrC | Page 52 of 76
ission is a 4-bit
trol registers (0x1B and
The length of the wait before data transm
programmable value in the link port con
0x1D Bits 6–3). This value allows the AD6652 PCLK and the
TigerSHARC PCLK to be run at different rates and out of
phase.
∫
×
≥
TSHARC
LCLK
AD
LCLK
ciel
WAIT
_
6652
_
6
WAIT ensures that the amount of tim
wait to begin data transmission is a
e the AD6652 needs to
t least equal to the minimum
f
igerSHARC is expecting it to wait. If the
LK of th
he PCLK of the
igerSHAR and the argument to the ceil() function is an
teger, the WAIT must be strictly greater than the value given
he abov formula.
he LCLK
data rate
amount o time the T
PC
e AD6652 is out of phase with t
T
C
in
n
in t
e
If t
s are in phase, then the maximum output
is
TSHARC
LCLK
AD
LCLK
_
6652
_
6
15
∫
×
≤
∫
therwise, is
O
it
TSHARC
LCLK
AD
_
6652
6
LCLK _
14
∫
×
≤
∫
TIGERSHARC CONFIGURATION
d
21. TigerSHARC LCTLx Register Configuration
egister
Value
Because the AD6652 is always the transmitter in this link an
the TigerSHARC is always the receiver, the following values can
be programmed into the LCTL register for the link port used to
receive AD6652 output data.
Table
R
VERE
0
SPD
User1
LTEN
0
PSIZE
1
TTOE
0
CERE
0
LREN
1
RTOE
1
e term U
s that the actual register value depends on the user’s
lication.
1 Th
ser mean
app
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