參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 64/76頁(yè)
文件大?。?/td> 1802K
代理商： AD6652XBC
Preliminary Technical Data
AD6652
Rev. PrC | Page 67 of 76
hen the
ter is loaded with the 16-bit value
c
nd
pin triggers the AGC hold-off counter with a
retriggerable one-shot pulse every time the pin is written high.
-bit binary floating-point
representation is used with a 2-bit exponent followed by the 6-
ps of 0.024 dB. A 12-bit
is used with a 4-bit
ntissa. For example:
be set from 0 to 0.996 in steps of 0.0039. This value of
K is updated in the AGC loop each time the AGC is initialized.
in the AGC loop each time the AGC
is initialized. This open loop pole location directly impacts the
to
Bits 5–2 define the scale used for the CIC filter.
2-bit register sets the AGC decimation ratio from 1 to
g factor to avoid loss of bits.
nk
is
A is enabled. The parallel
SPs or
ing
Bits 1–4. When Bit 0 = 1, Parallel
is
. In
8-bit Q word at the same time, and the IQ
Bit 0 is used to bypass the AGC section, when it is set. W
AGC is bypassed, the output data is the 16 MSBs of the 24-bit
input data from the half-band filter.
0x13: AGC B Hold-Off Counter
The AGC B hold-off coun
written to this address when Sync Now is written high or a
Pin_Sync signal is received. If this register is written to zero, the
AGC cannot be synchronized.
Note: The hold-off counter of AGC B shares the pin syn
assigned to DDC processing Channel 2. Therefore, if you inte
to use AGC A’s hold-off counter, you must either attach the
external sync signal to the pin sync that will be assigned to
DDC Channel 2, or use the software-controlled sync now
function of Bit 3 at 0x12.
The hold-off counter must be programmed with a 16-bit
number that corresponds to the desired delay before a new CIC
decimated value is updated. Writing a logic high to the proper
pin sync
0x14: AGC B Desired Level
This 8-bit register contains the desired output power level or
desired clipping level, depending on the mode of operation.
This desired request R level can be set from 0 dB to 23.99 dB
in steps of 0.094 dB. An 8
bit mantissa. The mantissa is in steps of 0.094 dB and the
exponent is in 6.02 dB steps. For example: 10’100101 represents
2 × 6.02 + 37 × 0.094 = 15.518 dB.
0x15: AGC B Signal Gain
This register is used to set the initial value for a signal gain used
in the gain multiplier. This 12-bit value sets the initial signal
gain between 0 dB and 96.296 dB in ste
binary floating-point representation
exponent followed by the 8-bit ma
0111’10001001 represents 7 × 6.02 + 137 × 0.024 + 45.428 dB.
0x16: AGC B Loop Gain
This 8-bit register is used to define the open loop gain K. Its
value can
0x17: AGC B Pole Location
This 8-bit register is used to define the open loop filter pole
location P. Its value can be set from 0 to 0.996 in steps of 0.0039.
This value of P is updated
closed loop pole locations as explained in the Automatic Gain
Control section.
0x18: AGC B Average Samples
This 6-bit register contains the scale used for the CIC filter and
the number of power samples to be averaged before being fed
the CIC filter.
Bits 1–0 define the number of samples to be averaged before
they are sent to the CIC decimating filter. This number can be
set between 1 and 4 with bit representation 00 meaning 1
sample and bit representation 11 meaning 4 samples.
0x19: AGC B Update Decimation
This 1
4096. Set an appropriate scalin
0x1A: Parallel Port Control A
Data is output through either a parallel port interface or a li
port interface. When 0x1B, Bit 7 = 0, the use of Link Port A
disabled and the use of Parallel Port
port provides different data modes for interfacing with D
FPGAs.
Bit 0 selects which data is output on Parallel Port A. When
Bit 0 = 0, Parallel Port A outputs data from the RCF accord
to the format specified by
Port A outputs the data from the AGCs according to the format
specified by Bits 1 and 2.
In AGC mode, Bit 0 = 1 and Bit 1 determines if Parallel Port A
able to output data from AGC A. Bit 2 determines if Parallel
Port A is able to output data from AGC B. The order of output
depends on the rate of triggers from each AGC, which in turn is
determined by the decimation rate of the channels feeding it
channel mode, Bit 0 = 0 and Bits 1–4 determine which
combination of the four processing channels is output. The
output order depends on the rate of triggers received from each
channel, which is determined by the decimation rate of each
channel. The channel output indicator pins can be used to
determine which data came from which channel.
Bit 5 determines the format of the output data words. When
Bit 5 = 0, Parallel Port A outputs 16-bit words on its 16-bit bus.
This means that I and Q data are interleaved, and the IQ
indicator pin determines whether data on the port is I data or
Q data. When Bit 5 = 1, Parallel Port A is outputting an 8-bit
I word and an
indicator pins are high.
0x1B: Link Port Control A
Data is output through either a parallel port interface or a link
port interface. The link port provides an efficient data link
between the AD6652 and a TigerSHARC DSP and can be
enabled by setting 0x1D, Bit 7 = 1.
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