參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 43/76頁(yè)
文件大小： 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 48 of 76
rporates two independent 16-bit parallel ports
transfer. To minimize package ball count, the
ive
ort be
PARALLEL OUTPUT PORTS
The AD6652 inco
for output data
eight LSBs of each 16-bit port are shared with their respect
DSP link port data bits (see Figure 45). This means that an
output port can transmit 16-bit parallel data or 8-bit link port
data, but not both. Transmitting both link and parallel data
simultaneously requires that the second AD6652 output p
configured for that purpose.
A
D
6
5
2
P
O
R
T
A
LINK PORT A CLOCK OUT
LINK PORT A CLOCK IN
LINK PORT A DATA OR 8 LSB'S
OF PARALLEL PORT A DATA
(SHARED PINS)
/
8
PCLK
PARALLEL PORT A MSB DATA
PARALLEL PORT A ACK
PARALLEL PORT A REQ
PARALLEL PORT A
CHANNEL INDICATOR
PARALLEL PORT A
I AND Q INDICATOR
/
8
/
2
A
D
6
5
2
P
O
R
T
B
LINK PORT B CLOCK OUT
LINK PORT B CLOCK IN
PCLK
LINK PORT B DATA OR 8 LSB'S
OF PARALLEL PORT B DATA
(SHARED PINS)
/
8
PARALLEL PORT B MSB DATA
PARALLEL PORT B ACK
PARALLEL PORT B REQ
PARALLEL PORT B
CHANNEL INDICATOR
PARALLEL PORT B
I AND Q INDICATOR
/
8
/
2
03198-0-041
Figure 45. Output Port Configuration
Each parallel output port has six data sources routed to it (see
the Functional Block Diagram in Figure 1):
Noninterpolated RAM coefficient FIR filter output data from
Channels 1, 2, 3, and 4
Interpolated, in
ed Channel A
data
any port(s). A port may
ut
A
in
configured using the
port clock control register at Ad ess 0x1E. Note that to access
these registers, Bit
ers) of External
Address 3 (sleep register) must be set. The address is then
l ports are enabled by setting Bit 7 of the link control
registers at Addresses 0x1B and 0x1D for Ports A and B,
respectively. Each parallel port is capable of operating in either
channel mode or AGC mode. These modes are described in
detail in the following sections.
CHANNEL MODE
Parallel port channel mode is selected by setting Bit 0 of
Addresses 0x1B and 0x1D for Parallel Ports A and B, respec-
tively. In channel mode, I and Q words from each channel are
directed to the parallel port, bypassing the AGC. The specific
channels output by the port are selected by setting Bits 1–4 of
Parallel Port Control Register 0x1A (Port A) and 0x1C (Port B).
Channel mode provides two data formats. Each format requires
a different number of parallel port clock (PCLK) cycles to
complete the transfer of data. In each case, each data element is
transferred during one PCLK cycle. See Figure 46 and Figure 47,
which present channel mode parallel port timing.
The 16-bit interleaved format provides I and Q data for each
output sample on back-to-back PCLK cycles. Both I and Q
words consist of the full port width of 16 bits. Data output is
triggered on the rising edge of PCLK when both REQ and ACK
are asserted. I data is output during the first PCLK cycle; the
PAIQ and PBIQ output indicator pins are set high to indicate
that I data is on the bus. Q data is output during the subsequent
PCLK cycle; the PAIQ and PBIQ output indicator pins are low
during this cycle.
terleaved, and/or AGC modifi
Interpolated, interleaved, and/or AGC modified Channel B
data
Any of the six sources may be output on
be configured to output parallel data or DSP link data. Outp
port control registers (Table 29) perform these multiplexing and
selection tasks.
Parallel port configuration is specified by accessing Port
Control Register Addresses 0x1A and 0x1C for Parallel Ports
and B, respectively. Port clock master/slave mode (described
dr
5 (access port control regist
selected by programming the CAR register at External
Address 6.
The paralle
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