參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 37/76頁(yè)
文件大小： 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 42 of 76
ion.
g
vel
e loop
ame way as the desired signal level mode. This
ation error is calculated and the AGC loop
vel is stored in the AGC desired level
is
in
desir
N
In in
recei
ronize the
era
exte
recei
chan
nization signal is connected to
(A, B, C, or D).
ynchroniza
se of an
ter. The hol
unter of AGC A sh
e pin sync that
ave assigne
DC processing Cha
Therefore, you
attach the e
l sync signal to the
nc chosen for
hannel 0.
ise, the hold-off cou
f AGC B
hares the pin synch that you have assigned to DDC processing
hannel 2. Therefore, you must attach the external sync signal
l be assigned to DDC Channel 2.
old-off counter register, 0x0B and 0x13 for AGC A and
, respectively, must be programmed with a 16-bit
ill
be co
is up
n
g
e
dow
r
e
Note
ro disables the hold-off
a
o
w
regis
,
when written high, performs an immediate start of decimation
and
ic
h
e
C
dela
Each
ew trigger event for the
ld-o
is
sign
Only
accu
C
cont
gered by either sync
Addr
r
conf
n
Tabl
resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC
control word. An error term (both I and Q) is generated that is
The h
AGC B
the difference between the signals before and after truncat
This term is passed to the complex squared magnitude block,
for averaging and decimating the update samples and takin
their square root to find rms samples, as in desired signal le
mode. In place of the request desired signal level, a desired
clipping level is subtracted, leaving an error term to be
processed by the second-order loop filter. The rest of th
operates the s
way, the trunc
operates to maintain a constant truncation error level.
Apart from Bit 4 of the AGC control words, the only register
setting changes compared to the desired signal level mode is
that the desired clipping le
reg ters (0x0C, 0x15) instead of the request signal level (as
ed signal level mode).
SY CHRONIZATION
stances where the AGC output is connected to a Rake
ver, a signal from the Rake receiver can synch
average-and-update section of the AD6652 to update the
av
ge power for AGC error calculation and loop filtering. This
rnal signal synchronizes the AGC changes to the Rake
ver and makes sure that the AGC gain word does not
ge over a symbol period and, therefore, more accurate
estimation. The external synchro
one or more of the pin sync pins
Pin s
tion requires the u
AGC hold-off
coun
d-off co
ares th
you h
d to D
nnel 0.
must
xterna
pin sy
DDC C
Likew
nter o
s
C
to the pin sync that wil
number that corresponds to the number of CLK cycles that w
unted ( a known delay) before a new CIC decimated value
dated. Writing a logic high to the proper pin sync pi
trig ers the AGC hold-off counter with a one-shot pulse every
tim the pin is written high. Once triggered, the counter counts
n to a value of one and then causes a start of decimation fo
a n w update sample.
: Setting the hold-off count to ze
counter. Setting the hold-off count to one provides the smallest
del y.
If y u choose not to use pin sync signals, you may use the Sync
No command through the microport. Each AGC control
ter has a sync now bit in Registers 0x0A:3 and 0x12:3 that
for a new update sample. This bit has a one-shot characteristic
does not need to be reset in order to respond to a new log
hig being written to it. Use of the sync now bit bypasses th
AG hold-off counters and performs sync functions without
y.
Pin Sync logic high initiates a n
ho
ff counter unless First Sync Only of the AGC’s control
reg ter (Bit 1) is set to logic high. When high, only the first sync
al is recognized and any others disregarded until First Sync
is reset.
Along with updating a new decimation value, the CIC filter
mulator can be reset if Init on Sync bit (Bit 2) of the AG
rol register is set. Init on Sync is trig
signal, pin sync, or sync now.
esses 0x0A to 0x11 have been reserved for configuring
AGC A and Addresses 0x12 to 0x19 have been reserved fo
iguring AGC B. The register specifications are detailed i
e 29.
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