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參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 34/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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AD6652
Preliminary Technical Data
Rev. PrC | Page 4 of 76
PRODUCT DESCRIPTION
The AD6652 is a mixed-signal IF to baseband receiver
consisting of dual 12-bit 65 MSPS ADCs and a quad-channel
multimode digital downconverter (DDC). The AD6652 is
designed to support communications applications where low
cost, small size, and versatility are desired. The AD6652 is also
suitable for other applications in imaging, medical ultrasound,
instrumentation, and test equipment.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Both
ADCs feature wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
ADC data outputs are internally connected directly to the
receiver’s digital downconverter (DDC) input matrix,
simplifying layout and reducing interconnection parasitics.
Overrange bits are provided for each ADC channel to alert the
user to ADC clipping. Level indicator bits are also provided for
each DDC input port that can be used for external VGA
control.
The digital receiver has four reconfigurable channels and
provides extraordinary processing flexibility. The receiver input
matrix routes the ADC data to individual channels, or to all four
receive processing channels. Each receive channel has five
cascaded signal processing stages: a 32-bit frequency translator
(numerically controlled oscillator (NCO)), two fixed-coefficient
decimating filters (CIC), a programmable RAM coefficient
decimating FIR filter (RCF), and an interpolating half-band
filter/AGC stage. Following the CIC filters, one, several, or all
channels may be configured to use one, several, or all the RCF
filters. This permits the processing power of four 160-tap RCF
FIR filters to be combined or used individually.
After FIR filtering, data can be routed directly to the two
external 16-bit output ports. Alternatively, data can be routed
through two additional half-band interpolation stages, where up
to four channels can be combined (interleaved), interpolated,
and processed by an automatic gain control (AGC) circuit with
96 dB range. The outputs from the two AGC stages are also
routed directly to the two external 16-bit output ports. Each
output port has a 16-bit parallel output and an 8-bit link port to
permit seamless data interface with DSP devices such as the
TS-101 TigerSHARC DSP. A multiplexer for each port selects
one of six data sources to appear on the device outputs pins.
The AD6652 is part of the Analog Devices SoftCell multimode
and multicarrier transceiver chipset. The SoftCell receiver
digitizes a wide spectrum of IF frequencies and then down-
converts the desired signals to baseband using individual
channel NCOs. The AD6652 provides user-configurable digital
filters for removal of undesired baseband components, and the
data is then passed on to an external DSP, where demodulation
and other signal processing tasks are performed to complete the
information retrieval process. Each receive channel is independ-
ently configurable to provide simultaneous reception of the
carrier to which it is tuned. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications. The decimating
filters remove unwanted signals and noise from the channel of
interest. When the channel occupies less bandwidth than the
input signal, this rejection of out-of-band noise is referred to as
processing gain. By using large decimation factors, this process-
ing gain can improve the SNR of the ADC by 20 dB or more. In
addition, the programmable RAM coefficient filter allows
antialiasing, matched filtering, and static equalization functions
to be combined in a single, cost-effective filter.
Flexible power-down options allow significant power savings,
when desired.
PRODUCT HIGHLIGHTS
Integrated dual 12-bit 65 MSPS ADC.
Four independent digital-filtering channels.
Proprietary, differential SHA input maintains excellent
SNR performance for input frequencies up to 200 MHz.
Crossbar-switched digital downconverter input ports.
Digital resampling permits noninteger relationships
between the ADC clock and the digital output data rate.
Energy-saving power-down modes.
32-bit NCOs with selectable amplitude and phase dithering
for better than 100 dBc spurious performance.
CIC filters with user-programmable decimation and
interpolation factors.
160-tap RAM coefficient filter for each DDC channel.
Dual 16-bit parallel output ports and dual 8-bit link ports.
8-bit microport for register programming, register read-
back, and coefficient memory programming.
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