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| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 15/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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AD6652
Preliminary Technical Data
Rev. PrC | Page 22 of 76
t the
output port(s) as a well-filtered, decimated digital baseband
signal:
12-bit A/D conversion
Frequency translation from IF to baseband using
quadrature mixers and NCOs
Second-order resampling decimating CIC FIR filter
(rCIC2)
Fifth-order decimating CIC FIR filter (CIC5)
RAM coefficient decimating FIR filter (RCF)
Automatic gain control (AGC)
2x interpolation and channel interleave
Any s
front
d
.
2’s capabilities.
The
diversity reception of signals,
wher
ntically on the same carrier
e user can sample
Hz using
C
hat
dual processing
d onto
,
ated
and control of the AD6652 is accomplished using
it
t
oltage boundary. ADC
outputs are internally routed to the input matrix of the DDC
st
r.
es
pipelined architecture permits the first stage to operate on a
new
ining stages operate on the
prec
rs on the rising edge of the
cloc
wide common-mode range;
HA is
the sample capacitors and settling within one-half
mic charging currents.
ass filter at the ADC’s
aci-
THEORY OF OPERATION
The AD6652 has two analog input channels, four digital filter-
ing channels, and two digital output channels. The IF input
signal passes through several stages before it appears a
tage may be bypassed with the exception of the ADC
end. Any combination of processing channels may be combine
or interleaved after the RCF stages to achieve demanding
filtering objectives that are not possible with just one channel
In the following sections, each stage is examined to allow the
user to fully utilize the AD665
dual ADC design is useful for
e the ADCs are operating ide
but from two separate antennae. The ADCs can also be
operated with independent analog inputs. Th
any fs/2 frequency segment from dc to 100 M
appropriate low-pass or band-pass filtering at the ADC inputs
with little loss in ADC performance. Operation to 200 MHz
analog input is permitted, but at the expense of increased AD
distortion.
In nondiversity applications, up to four GSM/EDGE-type
carriers may be concurrently processed from the ADC stage.
Wideband signals, such as WCDMA/CDMA2000, require the
power of two AD6652 processing channels per carrier to
adequately remove adjacent channel interference. When
diversity techniques are employed, the number of carriers t
may be processed is halved due to the
requirement of diversity reception.
Flexible channel multiplexing in the digital downconverter
(DDC) stage allows one to four channels to be interleave
one output port. Four synchronization input pins allow startup
frequency hop, and AGC functions to be precisely orchestr
with other devices. The NCO’s phase can be set to produce a
known offset relative to another channel or device.
Programming
an 8-bit parallel interface.
ADC ARCHITECTURE
The AD6652 front-end consists of two high performance, 12-b
ADCs, preceded by differential sample-and-hold amplifiers
(SHA) that provide excellent SNR performance from dc to
200 MHz. A flexible, integrated voltage reference allows analog
inputs up to 2 V p-p. Each channel is equipped with an
overrange pin that toggles high whenever the analog inpu
exceeds the upper or lower reference v
age for channel distribution. The ADC data outputs are not
directly accessible to the use
Each sample-and-hold amplifier (SHA) is followed by a pipe-
lined switched capacitor ADC. The pipelined ADC is divided
into three sections, consisting of a 4-bit first stage followed by
eight 1.5-bit stages and a final 3-bit flash. Each stage provid
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 12-bit result in the digital correction logic. The
input sample, while the rema
eding samples. Sampling occu
k.
Analog Input Operation
The analog inputs to the AD6652 are differential switched
capacitor SHAs that have been designed for optimum
performance while processing differential input signals. The
AD6652 accepts inputs over a
however, an input common-mode voltage, Vcm, of AVDD/2 is
recommended to maintain optimal performance and to
minimize signal-dependent errors.
Referring to Figure 31, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the S
switched into sample mode, the signal source must be capable
of charging
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dyna
This passive network creates a low-p
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt cap
tors should be removed. In combination with the driving source
impedance, the shunt capacitors would limit the input
bandwidth.
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