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| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 25/76頁 |
| 文件大小： | 1802K |
| 代理商： | AD6652XBC |
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Preliminary Technical Data
AD6652
Rev. PrC | Page 31 of 76
ED OSCILLATOR
has
en
LK
/2 with a resolution of CLK/232 in the complex
-case spurious signal from the NCO is better
uency programmed in registers 0x85 and 0x86 is
NUMERICALLY CONTROLL
FREQUENCY TRANSLATION TO BASEBAND
This processing stage comprises a digital tuner consisting of
two multipliers, I and Q, and a 32-bit complex numerically
controlled oscillator (NCO). Each channel of the AD6652
an independent NCO. The NCO serves as a quadrature local
oscillator capable of producing an NCO frequency betwe
CLK
/2 and +C
mode. The worst
than 100 dBc for all output frequencies.
The NCO freq
interpreted as a 32-bit unsigned integer. Use the following
equation to calculate the NCO frequency:
∫
×
=
CLK
FREQ
NCO
32
2
_
where:
NCO_FREQ is a decimal number equal to the 32-bit binary
number to be programmed at 0x85 and 0x86.
∫ is the desired NCO output frequency in Hz.
CLK is the AD6652 DDC master clock rate (in Hz).
NCO SHADOW REGISTER
A shadow register generally precedes an active register. It holds
the next number to be used by the active register whenever that
function’s hold-off counter causes the active register to be
updated with the new value. Active registers are also updated
with the contents of a shadow register any time the channel is
brought out of sleep mode.
The NCO shadow register is updated during normal program-
ming of the registers through the microport or serial input port.
The active frequency register can receive update data only from
the NCO shadow register. When software reads back an NCO’s
frequency, it is reading back the active frequency register and
not the shadow register.
NCO FREQUENCY HOLD-OFF REGISTER
When the NCO frequency registers are written, data is actually
passed to a shadow register. Data may be moved to the active
register by one of two methods: when the channel comes out of
sleep mode or when a SYNC hop occurs. As a result of either
event, a count-down counter is loaded with an NCO frequency
hold-off value. The 16-bit unsigned integer counter (0x84)
starts counting down at the DDC CLK rate and, when it reaches
one, the new frequency value in the shadow register is written to
the active NCO frequency register.
to
o
ple NCOs to be
u
a
ase differences.
O CONTROL REGISTER
e the NCO control r ister located at 0x88
ure the
atures of the NCO, which are controlled on a per channel
basis. These features are described in the following sections.
Bypass
To bypass the NCO of the AD6652, set Bit 0 of 0x88 high.
When the NCO is bypassed, down-conversion is not performed,
and the AD6652 channel functions simply as a real filter on
complex data. This feature is useful for baseband sampling
applications, where the A input is connected to the I signal path
within the filter and the B input is connected to the Q signal
path. Bypassing the NCO may be desired, if the digitized signal
has already been converted to baseband in prior analog stages
or by other digital preprocessing.
Phase Dither
The AD6652 provides a phase dither option for improving the
spurious performance of the NCO. To enable phase dither, set
Bit 1 of Register 0x88, which causes discrete spurs due to phase
truncation in the NCO to be randomized. The energy from
these spurs is spread into the noise floor and spurious free
dynamic range is increased at the expense of slight decreases in
the SNR. The choice of whether to use phase dither in a system
depends ultimately on the system goals. If lower spurs are
desired at the expense of a slightly raised noise floor, then phase
dither should be employed. If the lowest noise floor is desired
and higher spurs can be tolerated or filtered by subsequent
stages, then phase dither is not needed.
Amplitude Dither
Amplitude dither can also be used to improve spurious
performance of the NCO. To enable amplitude dither, set Bit 2
of 0x88, which causes amplitude quantization errors to be
randomized within the angular-to-Cartesian conversion stage
of the NCO. This option may reduce spurs at the expense of a
slightly raised noise floor and slightly reduced SNR. Amplitude
dither and phase dither can be used together, separately, or not
at all.
The NCO can be set up to update its frequency immediately
upon receipt of a HOP_SYNC or START_SYNC, with no
hold-off count, by setting the hold-off count value to 1. Setting
the hold-off count to zero prevents any frequency updates.
PHASE OFFSET
The phase offset register (0x87) adds a programmable offset
the phase accumulator of the NCO. This 16-bit register is
interpreted as a 16-bit unsigned integer. A 0x0000 in this
register corresponds to no offset, and a 0xFFFF corresponds t
an offset of 2π radians. This register allows multi
synchronized to prod ce outputs with const nt and known
ph
NC
Us
eg
to config
fe
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