參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 51/76頁(yè)
文件大?。?/td> 1802K
代理商： AD6652XBC
Preliminary Technical Data
AD6652
Rev. PrC | Page 55 of 76
l
ay
riting this bit to logic high enables
e
ach
he
re
r
s bit
this
es
e written to Logic 0.
ing this bit also programs the Channel Address Register 0x82
d sh
ritten to Logic 0.
Bit 5 allows access to the output control port registers. When
emory structure.
from both of these
be calculated. Multiple
s to
r
ired.
tten logic high.
PIN_SYNC CONTROL REGISTER
External Address 4
This is the write-only PIN_SYNC control register.
Bits 3–0 of this register are the PIN SYNC_EN control bits.
These bits may be written to by the controller to select any or al
of the external pin sync inputs: A, B, C, and/or D. One pin m
be assigned to all channels, one pin may be assigned to one
channel, or any combination in between. This register is fully
configurable at the channel level (in the channel address register
memory map, 0x88) as to which pin-sync signal is selected. A
pin-sync signal may be used in addition to a soft-sync signal, if
desired. See Figure 44.
Bit 4 is the Start enable bit. W
or facilitates the routing of the external pin-sync signal to all th
DDC channels. This bit enables any pin-sync signals that were
selected by Bits 3–0 above, to be routed to a 4-to-1 multiplexer
and ultimately chosen to be the channel’s pin-sync signal that
controls the Start function. See Figure 44. Programming this bit
also programs the Channel Address Register 0x82 of e
channel.
Bit 5 is the Hop enable bit. Writing this bit to logic high enables
or facilitates the routing of the external pin-sync signal to all t
DDC channels. This bit enables any pin-sync signals that we
selected by Bits 3–0 above to be routed to a 4-to-1 multiplexe
and ultimately chosen to be the channel’s pin-sync signal that
controls the Hop function. See Figure 44. Programming thi
also programs the Channel Address Register 0x82 of each
channel.
Bit 6 is used to ignore repetitive synchronization signals. If
bit is clear, each PIN_SYNC restarts or frequency hops the
channel. If this bit is set, then only the first occurrence caus
the action to occur. Programming this bit also programs the
Channel Address Register 0x82 of each channel.
Bit 7 is reserved; the bits should b
SLEEP CONTROL REGISTER
External Address 3
In addition to sleep mode control, this register also provides
access to the output port control registers memory map.
Bits 3–0 control the sleep mode of the indicated channel. If the
bit is low, the channel operates normally. If the bit is high, the
indicated channel enters a low-power sleep mode. Program-
m
of each channel.
Bit 4 is reserved an
ould be w
this bit is low, the channel address registers are accessed.
However, when this bit is set high, it allows access to the output
port control registers. When this bit is set high, the value in
External Address 6 (CAR) points to the memory map for the
output control port registers instead of the normal channel
address register memory map. See Table 29 in the Output Port
Bit 6–7 are reserved and should be written low.
DATA ADDRESS REGISTERS
External Address 2–0
These registers form the data registers DR2, DR1, and DR0,
respectively. All internal data words have widths that are equal
to or less than 20 bits. When External Address 0 is written to, it
triggers an internal access to the AD6652 based on the address
indicated in the ACR and CAR. Thus, during writes to the
internal registers, External Address [0] DR0 must be written
last. At this point data is transferred to the internal memory
indicated in A[9:0]. Reads are performed in the opposite
direction. Once the address is set, External Address [0] DR0
must be the first data register read to initiate an internal access.
DR2 is only 4 bits wide. Data written to the upper 4 bits of this
register are ignored. Likewise, reading from this register
produces only 4 LSBs.
Figure 54 is a block diagram of the m
CHANNEL ADDRESS REGISTERS (CAR)
0x00–0x7F: Coefficient Memory (CMEM)
This register is the coefficient memory (CMEM) used by the
RCF. It is memory mapped as 128 words by 20 bits. A second
128 words of RAM may be accessed via this same location by
writing Bit 8 of the RCF control register high at Channel
Address 0xA4. The filter calculated always uses the same
coefficients for I and Q. By using memory
128 blocks, a filter up to 160 taps can
filters can be loaded and selected with a single internal acces
the coefficient offset register at Channel Address 0xA3.
0x80: Channel Sleep Register
This register contains the sleep bit for the channel. It mimics the
programming of Bits 0–3 at External Address 3. External
Address 3 provides simultaneous sleep mode control for all fou
DDC channels. You may overwrite the data in 0x80, if des
Sleep mode is selected when this bit is wri
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