參數(shù)資料
型號(hào)： AD6652XBC
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁(yè)數(shù)： 19/76頁(yè)
文件大?。?/td> 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 26 of 76
rate. Normal ADC operation
asing
tion.
d REFB are discharged
then must be recharged when
s
e
ADC Power-Down Mode
e AD6652 front end ADC is
ADC Wake-Up Time
The power dissipated by th
proportional to its sampling
requires that both PDWN pins be set to logic low. The ADC
can be placed in a power-down mode by setting both PDWN
pins to logic high. Low power dissipation in power-down mode
is achieved by shutting down the reference buffers and bi
networks of both ADC channels. Both power-down pins must
be driven together either high or low for proper ADC opera
For maximum power savings, the ACLK and analog input(s)
should remain static while in standby mode, resulting in a
typical power consumption of 1 mW for the ADC. If the clock
inputs remain active while in standby mode, typical power
consumption for the ADC is 12 mW.
The decoupling capacitors on REFT an
when entering standby mode, and
returning to normal operation. As a result, the wake-up time i
related to the time spent in standby mode. Shorter standby
cycles result in proportionally shorter wake-up times. With th
recommended 0.1 F and 10 F decoupling capacitors on REFT
and REFB, it takes approximately 1 s to fully discharge th
reference buffer decoupling capacitors, and 5 ms to restore full
operation.
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