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參數(shù)資料
| 型號： | AD6652XBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, MINI, BGA-256 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | AD6652XBC |
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Preliminary Technical Data
AD6652
Rev. PrC | Page 57 of 76
NCO control register at Channel Address 0x88. When this bit is
w, then the phase acc mulator of the NCO is not cleared but
tarts to add the new N O frequency word to the accumulator
s soon as the SYNC occurs. If this bit is high, then the phase
ccumulator of the NCO is cleared to 0 and the new word is
p
as been issued. In the
dated when the frequency
d-of
nt reaches a value of one. If the frequency
hold-of
ounter v
, then the register is
updated
on a
0x86: NCO Frequency Register 1
cy
adowed and are not updated to the
he channel is either brought out of sleep
Soft_SYNC or Pin_SYNC has been issued. In the
when the frequency
Channel Address
Register
Bit Wid
lo
u
s
C
a
then accumulated.
0x85: NCO Frequency Register 0
This register represents the 16 LSBs of the NCO frequency
word. These bits are shadowed and are not updated to the
working register until the channel is either brought out of slee
mode, or a Soft_SYNC or Pin_SYNC h
latter two cases, the register is up
hol
f counter cou
f c
alue is set to a value of 1
as so
s the shadow is written.
This register represents the 16 MSBs of the NCO frequen
word. These bits are sh
working register until t
mode, or a
latter two cases, the register is updated only
hold-off counter count reaches a value of one. If the frequency
hold-off counter is set to a value of 1, then the register is
updated as soon as the shadow is written.
Table 24. Channel Address Memory Map
th
Comments
00-7F
Coefficient Memory (CMEM)
20
128 x 20-bit memory
80
CHANNEL SLEEP
1
0:
Sleep bit from EXT_ADDRESS 3
81
Soft_Sync Control Register
2
1:
Hop
0:
Start
82
Pin_SYNC Control Register
3
2:
First SYNC only
1:
Hop_En
0:
Start_En
83
Start Hold-Off Counter
16
Start hold-off value
84
NCO Freq
nter
16
uency Hold-Off Cou
NCO_FREQ hold-off value
85
NCO Frequency Register 0
16
NCO_FREQ[15:0]
86
NCO Frequency Register 1
16
1:16]
NCO_FREQ[3
87
NCO Phase Offset Register
16
NCO_PHASE[15:0]
88
NCO Control Register
9
8-7:
SYNC input select[1:0]
00 = A, 01 = B, 10 = C, 11 = D
6:
Input port select B or A, 0 = A, 1 = B
5-4:
Reserved, write both bits logic low
on hop
3:
Clear phase accumulator
2:
Amplitude dither
1:
Phase dither
0:
Bypass (A-input -> I-path, B -> Q)
89-8F
Unused
90
rCIC2 Decimation 1
12
MrCIC2 1
91
rCIC2 Interpolation 1
9
LrCIC2 1
92
rCIC2 Scale
12
11:
Reserved, write to logic low
10:
rCIC2 _QUIET [4:0]
9-5:
4-0:
rCIC2_LOUD [4:0]
93
Reserved
8
Reserved (must be written low)
94
CIC5 Decimation 1
8
MCIC5 1
95
CIC5 Scale
5
4-0:
CIC5_SCALE[4:0]
96
Reserved
8
ust be written low)
Reserved (m
97-9F
Unused
A0
RCF Decimation 1
8
MRCF 1
A1
RCF Decimation Phase
8
PRCF
A2
RCF Number of Taps 1
8
ps
1
NTa
A3
RCF Coefficient Offset
8
CORCF
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