參數(shù)資料
型號： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁數(shù)： 58/76頁
文件大?。?/td> 1802K
代理商： AD6652XBC
Preliminary Technical Data
AD6652
Rev. PrC | Page 61 of 76
trol r
ious input-related
ures used primarily f
ending on the
f operation, up
paths can be
tored with these r
atures are accessed
ing Bit 5 of Externa
then
g the CAR (External Address 6) to address the 8 locatio
vailable. Response to t ese settings is directed to the LIA, L
INPUT PORT CONTROL REGISTERS
The input port con
egisters enable var
feat
mode o
or level control. Dep
to 4 different signal
moni
egisters. These fe
by
sett
l Address 3 (sleep register) and
usin
ns
a
h
IA,
, and LIB
LIB
pins.
ccess the input po
rogram gain control
uld be written high
he
ddress to the correct input port register.
his word is 10 bits wide and maps to the 10 MSB of the
s than or
been met. In
r
iate LI pin (LIA
or LIA
To a
rt registers, the p
bit
sho
. The CAR is then written with t
a
0x00: Lower Threshold A
T
mantissa. If the upper 10 bits of Input Port A are les
equal to this value, then the lower threshold has
normal chip operation, this starts the dwell time counter. If the
input signal increases above this value, then the counter is
reloaded and awaits the input to drop back to this level.
0x01: Upper Threshold A
This word is 10 bits wide and maps to the 10 MSB of the
mantissa. If the upper 10 bits of Input Port A are greater than o
equal to this value, then the upper threshold has been met. In
normal chip operation, this causes the appropr
) to become active.
w
t to at
unctions are disabled. This is a 20-bit
threshold is met following an
me counter is
eed clock cycles as long as
0x02: Dwell Time A
This word sets the time that the input signal must be at or belo
the lower threshold before the LI pin is deactivated. For the
input level detector to work, the dwell time must be se
least 1. If set to 0, the LI f
register. When the lower
excursion into the upper threshold, the dwell ti
loaded and begins to count high sp
the input is at or below the lower threshold. If the signal
increases above the lower threshold, the counter is reloaded and
waits for the signal to fall below the lower threshold again.
0x03: Gain Range A Control Register
Bit 4 determines the polarity of LIA andLIA. If this bit is clear,
then the LI signal is high when the upper threshold has been
Bit 2–0 determines the internal latency of the gain detect
fu
the LIA, LIA
exceeded. However, if this bit is set, the LI pin is low when
active. This allows maximum flexibility when using this
function.
Bit 3 = 0 (Reserved).
nction. When
pins are made active, they are
ty
us
gain stage. Because
th
rior
sociated with the
A
w
ister
al
s the i
pically
ed to change an attenuator or
is is p
to the ADC, there is a latency as
DC and ith the settling of the gain change. This reg
low
nternal delay of the LIA, LIA signal to be
pr
amme
0x04: Lower Threshold B
T
rd i
e 10 MSB of the
m
If
han or
eq
to thi
old has been met. In
no
al chip
ell time counter. If the
in
gnal in
the counter is
re
d an
o this level.
0x05: Upper Threshold B
rt B are greater than or
ogr
d.
his wo
s 10 bits wide and maps to th
antissa.
the upper 10 bits of Input Port B are less t
ual
s value, then the lower thresh
rts the dw
rm
operation, this sta
put si
loade
creases above this value, then
d awaits the input to drop back t
This word is 10 bits wide and maps to the 10 MSB of the
mantissa. If the upper 10 bits of Input Po
equal to this value, then the upper threshold has been met. In
normal chip operation, this causes the appropriate LI pin (LIB
or LIB) to become active
0x06: Dwell Time B
This word sets the time that the input signal must be at or below
the lower threshold before the LI pin is deactivated. For the
t
count high speed clock cycles as long as
hreshold. If the signal
nd
Range B Control Register
and LIB
input level detector to work, the dwell time must be set to a
least 1. If set to 0, the LI functions are disabled. This is a 20-bit
register. When the lower threshold is met following an
excursion into the upper threshold, the dwell time counter is
loaded and begins to
the input is at or below the lower t
increases above the lower threshold, the counter is reloaded a
waits for the signal to fall below the lower threshold again.
0x0: Gain
Bit 4 determines the polarity of LIB
. If this bit is clear,
then the LI signal is high when the upper threshold has been
exceeded. However, if this bit is set, the LI pin is low when
active. This allows maximum flexibility when using this
function.
Bit 3 = 0 (Reserved.
Bit 2–0 determines the internal latency of the gain detect
function. When the LIB, LIB pins are made active, they are
typically used to change an attenuator or gain stage. Because
this is prior to the ADC, there is a latency associated with the
ADC and with the settling of the gain change. This register
allows the internal delay of the LIB, LIB signal to be
programmed.
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