參數(shù)資料
型號(hào)： AD6652XBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, MINI, BGA-256
文件頁數(shù)： 41/76頁
文件大?。?/td> 1802K
代理商： AD6652XBC
AD6652
Preliminary Technical Data
Rev. PrC | Page 46 of 76
e
ync pins
Start with Pin Sync
The AD6652 provides four SYNC pins. A, B, C, and D, which ar
used for very accurate channel synchronization. Each DDC
channel can be programmed to respond to any or all four sync
pins. Synchronization of start with one of the external s
is accomplished with the following method. Refer to Figure 44
to assist in following this process.
1.
Place the channels to be programmed in sleep mode. The
AD6652 RESET pin places all four DDC processing
channels in sleep mode when toggled low mome tar
n
ily.
els have not been completely
3.
ress 4:4) and choose
4.
his is
done at Address 0x88:8–7. Table 20 is the truth table for
these bits.
Table 20. Truth Table
Pin Selected
2.
Write the start hold-off counter(s) (0x83) to a value from 1
to 216 1. If the chip or chann
programmed, write all other registers now.
Set the Start_En bit high (External Add
which Pin Sync_En bits (External Address 4:3–0) are to be
used. Write the bit high to enable it.
Set the sync input select bits for each active channel. T
0x88:8
0x88:7
Sync
0
A
0
1
B
1
0
C
1
D
After programming is complete and when the external signal
attached to the selected sync pin goes high, this triggers the start
hold-off counter of the chosen channel(s). The hold-off counter
begins counting using the AD6652 CLK signal. When it reaches
a count of one, the sleep bit of the selected channel(s) is set low
to awaken the channel(s). Each Pin Sync logic high initiates a
new trigger event for the hold-off counter unless First Sync
Only, External Address 4:6 is set to logic high. When high, only
the first sync signal is recognized and any others are disre-
garded until First Sync Only is reset.
Note: Each channel has a redundant pin-sync control register at
Address 0x82. This register mimics the programming as set in
External Memory Address 4:6–4. You may control the pin sync
function of an DDC channel by writing to Registers 0x82 and
0x88:8–7, if it is advantageous to do so in your application.
rol
g the channel from sleep mode generates an
internal start command that performs both hop and start
microport. The NCO frequency hold-off counter (0x84) in
(number of AD6652
LKs). Use the following method to synchronize a hop in
requency of multiple channels via microprocessor control:
1.
Write the NCO frequency hold-off counter (0x84) to the
appropriate value (greater than 0 and less then 216).
2.
Write the NCO Frequency Register(s), 0x85 and 0x86, to
the new desired frequency.
3.
Write the hop bit and the applicable channel sync bit(s)
high at External Address 5.
This triggers the frequency hold-off counter(s) to begin their
count. The counters are clocked with the AD6652 CLK signal.
When it reaches a count of one, the new frequency data is
transferred from the shadow register to the working register of
the NCO. Unlike the start function, the channels do not need to
be placed in sleep mode to achieve a frequency hop.
Note: Each channel has a redundant soft-sync control register at
address 0x81. This register mimics the programming as set in
the External Memory Address 5:5–4. You may control the soft-
sync function of a DDC channel by writing to the 0x81 register,
if it is advantageous to do so in your application.
Note that the time from when the DTACK
Note that the time from when the pin sync goes high to when
the DDC channel resumes processing is equal to the time
period set up by the start hold-off counter value at 0x83 +
3 CLK cycles.
HOP
Hop is a change from one NCO frequency to a new NCO
frequency. This may apply to a single channel or multiple
channels and can be synchronized via microprocessor cont
(soft sync) or an external sync signal (pin sync), as described
below. Awakenin
functions as if a soft-sync or pin-sync had been received.
Hop with Soft Sync
The AD6652 includes the ability to synchronize a change in
NCO frequency of multiple channels or chips using the
conjunction with the hop bit and the sync bit (External
Address 4) allows this synchronization. Basically, the NCO
frequency hold-off counter delays the new frequency from
being loaded into the NCO by its value
C
f
pin goes high (which
acknowledges the receipt of the soft sync command data) to
when the DDC channel begins processing data is equal to the
time period set up by the frequency or hop hold-off counter
value at 0x84 + 7 CLK cycles.
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