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參數資料
| 型號： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁數： | 113/155頁 |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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60
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
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empty bit UASx TSx. Transmission resumes and the UASx TSx is cleared when a new char-
acter is loaded in the transmitter holding register.
If the transmitter is disabled, it will continue operating until the character currently being transmit-
ted is completely sent out. The transmitter holding register cannot be loaded when the
transmitter is disabled.
If flow control is enabled, the CTS input must be low in order for the character to be transmitted.
If it is deasserted in the middle of a transmission, the character in the shift register is transmitted
and the transmitter serial output then remains inactive until CTS is asserted again. If the CTS is
connected to a receivers RTS, overrun can effectively be prevented.
Receiver Operation
The receiver is enabled for data reception when the receiver enable bit UACx REx is set logical
one. The receiver looks for a high to low transition of a start bit on the receiver serial data input
pin. If a transition is detected, the state of the serial input is sampled a half bit clocks later. If the
serial input is sampled high the start bit is invalid and the search for a valid start bit continues. If
the serial input is still low, a valid start bit is assumed and the receiver continues to sample the
serial input at one bit time intervals until the proper number of data bits and the parity bit have
been assembled and one stop bit has been detected. During this process the least significant bit
is received first.
The serial input is sampled three times for each bit and averaged to filter out noise.
The data is then transferred to the receiver holding register and the data ready bit UASx DRx is
set logical one. The parity, framing and overrun error bits are set at the received byte boundary,
at the same time as the receiver ready bit is set.
If both receiver holding and shift registers contain an un-read character when a new start bit is
detected, then the character held in the receiver shift register will be lost and the overrun bit
UASx OVx is set logical one.
If flow control is enabled, then the RTS will be negated (high) when a valid start bit is detected
and the receiver holding register contains an un-read character. When the holding register is
read, the RTS will automatically be reasserted again.
A correctly received byte is indicated by the data ready bit UASx DRx. In case of error (framing
error, stop bit error,...), the respective bits UASx FEx, UASx PEx, ... are set logical one when
the data ready bit remains logical zero.
Interrupt Generation
The two UARTs can be configured to generate interrupt each time a byte is received or a byte is
sent.
If the UACx TIx is set logical one, an interrupt is issued after each character sending. If set log-
ical zero, no interrupt is issued on character sending.
If the UACx RIx is set logical one, an interrupt is issued after each character reception. If set
logical zero, no interrupt is issued after a character reception.
If the receiver interrupt is enabled, when error is detected during the reception of a character,an
interrupt is generated. To identify the origin of the transaction failure, refer to the uart status reg-
ister bits (UASx OVx, UASx PEx, UASx TEx) that indicate either it is a parity, a framing or
an overrun error.
Loop back mode
If the UACx LBx is set, the UART will be in loop back mode. In this mode, the transmitter output
is internally connected to the receiver input and the RTS is connected to the CTS. It is then pos-
sible to perform loop back tests to verify operation of receiver, transmitter and associated
software routines. In this mode, the outputs remain in the inactive state, in order to avoid send-
ing out data.
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相關代理商/技術參數 |
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| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
| 5962R0722701VZA | 功能描述:模數轉換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0722961VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0724902VPC | 制造商:Intersil Corporation 功能描述: |
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