參數(shù)資料
型號(hào): 5962R0722402VYC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝: QFP-256
文件頁數(shù): 85/155頁
文件大?。?/td> 4139K
代理商: 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
35
7703D–AERO–12/09
PR
ELI
MINA
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Y
IN
FOR
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AT
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PROM Interface
Overview
The memory controller give the capability to control up to 512Mbyte of PROM. The PROM inter-
face can manage up to two PROM banks. The control of the PROM memory accesses uses a
standard set of pin, including chip selects (ROMS*x), output enable (OE*), read (READ) and
write (WRITE*) lines.
The bank size of the PROM banks is not programmable. The lower half part of the PROM area
(0x00000000 up to 0x0FFFFFFF) is controlled by the ROMS0* PROM select signal. The upper
half part of the PROM area (0x10000000 up to 0x1FFFFFFF) is controlled by the ROMS1*
PROM select signal.
PROM Read Access
A read access to PROM consists in two data cycles and waitstates if any programmed. On non-
consecutive accesses, a lead-out cycle is added after a read transaction to prevent bus conten-
tion due to slow turn-off time of memories or I/O devices. On consecutive accesses, no lead-out
cycle is performed between the acesses but only one is performed at the end of the operations.
Figure 18. PROM Read transaction (0 Waitstate)
data1
data2
D1
lead-out
A1
CLK
A
ROMS*
D
OE*
PROM Write Access
Each write access to PROM consists of three states and of waitstates if any programmed. The
three mandatory states are divided in one write setup cycle, one data cycle and one lead-out
cycle. The write operation is strobed by the WRITE* signal.
Figure 19. PROM Write transaction (0 waitstate)
lead-in
data
lead-out
D1
A1
CLK
A
ROMS*
D
WRITE*
Waitstates
For application using slow ROM memories, the ROM controller provides the capability to insert
wait-states during the accesses. Two types of wait-states can be inserted :
Programmed delay
‘Hardware’ bus ready delay
Up to 30 waitstates can be programmed for PROM accesses. Read and write waitstates can be
individually programmed. Setting MCFG1 PRRWS defines the number of waitstates to insert
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