參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 97/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
46
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
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If a data sub-block parity error occurs, a miss is also generated but only the failed sub-block is
updated with data from main memory. Each error is reported in the data cache data error coun-
ter from the CCR. CCR DDE is incremented after each data cache data error detection.
Data Cache Snooper
In addition to the cache controller, a snooper is implemented on the on-chip cache subsystem.
The cache snooper is enabled setting logical one in CCR DS.
This snooper is able to verify if a master on the internal bus accesses and modifies some
cached data. If a master accesses a data in memory and this data is cached, the snooper will
invalidate the corresponding cache tag. Next time the IU will access the modified data, a cache
miss will be generated due to not valid tag.
Diagnostic Cache
Access
Tags and data in the instruction and data cache can be accessed through ASI address space
0xC, 0xD, 0xE and 0xF by executing LDA and STA instructions. Address bits making up the
cache offset will be used to index the tag to be accessed while the least significant bits of the bits
making up the address tag will be used to index the cache set.
Diagnostic read of tags is possible by executing an LDA instruction with ASI=0xC for instruction
cache tags and ASI=0xE for data cache tags. The cache line and the cache set are indexed by
the address bits making up the cache offset and the least significant bits of the address bits
making up the address tag.
Similarly, the data sub-blocks may be read by executing an LDA instruction with ASI=0xD for
instruction cache data and ASI=0xF for data cache data. The sub-block to be read in the
indexed cache line and set is selected by A[4:2].
The tags can be directly written by executing a STA instruction with ASI=0xC for the instruction
cache tags and ASI=0xE for the data cache tags. The cache line and cache set are indexed by
the address bits making up the cache offset and the least significant bits of the address bits
making up the address tag.
D[31:10] is written into the ATAG filed and the valid bits are written with the D[7:0] of the write
data. The data sub-blocks can be directly written by executing a STA instruction with ASI=0xD
for the instruction cache data and ASI=0xF for the data cache data. The sub-block to be read in
the indexed cache line and set is selected by A[4:2].
Note:
Diagnostic access to the cache is not possible during a FLUSH operation and will cause a data
exception (trap=0x09) if attempted.
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