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| 型號(hào)： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁(yè)數(shù)： | 76/155頁(yè) |
| 文件大小： | 4139K |
| 代理商： | 5962R0722402VYC |
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AT697F PRELIMINARY INFORMATION
27
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
RAM Interface
The memory controller gives the capability to control up to 1Gbyte of RAM. The global RAM area
supports two RAM types : asynchronous static RAM (SRAM) and synchronous dynamic RAM
(SDRAM).
SRAM interface
Overview
The SRAM interface can manage up to five SRAM banks. The control of the SRAM memory
accesses uses a standard set of pin, including chip selects (RAMS*x), output enable
(RAMOE*x) and write enable (RWE*x) lines.
The bank size of the four first banks of the SRAM area can be configured by setting the value of
MCFG2
RAMBS. The bank size can be programmed in binary step from 8 Kbytes to 256
Mbytes. Whatever is the size of the four first banks, they are always contiguous. These memory
banks are selected with RAMS*[3] down to RAMS*[0].
The fifth SRAM bank controlled by RAMS*[4] has a fix dimension. This bank always resides at
the upper address 0x60000000. This bank is always 256 Mbytes large.
Figure 9. SRAM bank organisation
SRAM bank size
256MB
128MB
64MB
Start Address
Memory
assignement
Memory
assignement
Memory
assignement
0x7C000000
Unused
0x78000000
0x74000000
0x70000000
0x6C000000
RAMS*[4](1)(2)
RAMS*[4](2)
0x68000000
0x64000000
0x60000000
0x5C000000
RAMS*[1]
RAMS*[3]
Unused
0x58000000
0x54000000
RAMS*[2]
0x50000000
0x4C000000
RAMS*[0]
RAMS*[1]
RAMS*[3]
0x48000000
RAMS*[2]
0x44000000
RAMS*[0]
RAMS*[1]
0x40000000
RAMS*[0]
Notes:
1. If the SRAM bank size is set to 256Mbytes, SRAM bank 2 & bank 3 are in overlay with SRAM
bank 4. In this case, bank 2 and bank 3 control signals are never asserted. Bank 4 has the
priority.
2. When SDRAM is enabled, priority is given to the SDRAM. Any access to addresses higher
than 0x60000000 is driven to SDRAM. No SRAM control is activated.
SRAM Read Access
A read access to SRAM consists in two data cycles and between zero and three waitstates. On
non-consecutive accesses, a lead-out cycle is added after a read cycle to prevent bus conten-
tion due to slow turn-off time of memories or I/O devices. On consecutive accesses, no lead-out
cycle is performed between the acesses but only one is performed at the end of the operations
(RAMSN and RAMOE are not deasserted).
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