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參數(shù)資料
| 型號： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁數(shù)： | 103/155頁 |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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AT697F PRELIMINARY INFORMATION
51
7703D–AERO–12/09
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PCI Arbiter
A PCI arbiter is embedded on the AT697 chip. The¨PCI arbiter enables the arbitration of 4 PCI
agents numbered from 3 downto 0. A round-robin algorithm is implemented as arbitration policy.
The PCI arbiter is totally independent from the PCI interface
Operation
An Agent on the PCI bus requests the bus by driving low its REQ* line. When the arbiter deter-
mines that the bus can be granted to an agent, it drives low the corresponding GNT* line.
When the bus is granted to a PCI agent, the agent keeps the bus for only one transaction. If the
agent desires more accesses, it shall continue to assert its REQ* line and wait to be granted the
bus again.
Round Robin
The round robin algorithm used for the arbitration is based on various loops with different priority
levels. The implementation in the AT697 is based on two priority loops. A high priority loop is
defined as level 0. A low priority loop is defined as level 1.
Operation
The arbitration is done checking the REQ* lines of the PCI agents one after each other. In first
place, the loop with level 0 is checked. If a a REQ* is active and no master is currently granted
ther bus, the corresponding GNT* line is driven low. Then, the agent is granted the bus. At each
complete round-turn in level 0, one step is done in level 1. The following figure illustrates the
operation of the arbitre.
Figure 35. Arbitre operation - Agent
Agent 0 Agent 1
Agent 2
Agent 3
Agent 0 Agent 1
level 0
level 1
time
With : agents 0 and 1 at level 0
agents 2 and 3 at level 1
If all agents have a request at the same time, the following probabilities of access are
implemented:
All agents in one level have equal probability
All agents in level 1 together have the same probability of access as one agent in level 0.
If no agent is in level 0, or no agent in level 0 has a request, all agents in level 1 are granted
with equal probability
Bus Parking
As long as no bus request is active on the arbiter, the bus is granted to the last owner. It remains
granted to the last owner until another agent requests the bus. When another request is
asserted, re-arbitration occurs after one turnover cycle.
After reset, the bus is parked to agent 0. Agent 0 is the default owner after a reset operation.
Re-arbitration
When a master is managing a transfer and another one makes a request to the arbiter, re-arbi-
tration occurs. Only one re-arbitration is performed during a transfer. A new arbitration will take
place when the master which was granted the bus frees the bus. As long as all the PCI agents
have no request pending, the arbitration is performed. A re-arbitration cycle also occurs when
living the bus parking state.
Priority definition
Two different priority levels are defined for the PCI arbiter. Level 0 is defined as the high priority
level. Level 1 defines the low priority level. Assignment of the PCI agents priority level is pro-
grammable through the arbiter configuration register (ACR).
Each PCI agent can be individually configured to operate either on level 0 or on level 1, except
agent 3 that is defined by hardware with a low priority (level 1).
Setting logical one in PCIA Px leads the agents x to a low priority level. Setting this bit logical
zero leads to a high priority.
After reset, all the PCI agents are configured in the low priority loop.
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