參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 98/155頁
文件大?。?/td> 4139K
代理商： 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
47
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Timer Unit
Prescaler
Timer/Counter1, Timer/Counter2 and the watchdog share the same prescaler.
The prescaler consists of a 10-bit down counter clocked by the system clock. The prescaler is
decremented on each clock cycle. When the prescaler underflows, it is automatically reloaded
with the content of the prescaler reload register. A count tick is generated for the two timers and
the watchdog.
The effective division rate is equal to prescaler reload register value + 1.
Figure 30. Prescaler Block Diagram
Control Logic
Reload Reg.
Counter Reg.
=0x3FF
clock
count tick
load
SCAR
SCAC
Da
ta
B
u
s
Note:
The reset value for SCAR is 0. This is not a legal value, it is however equivalent to a value of 3
and leads to a division rate of 4.
Caution :
The two timers and watchdog share the same decrementer. The minimum allowed prescaler
division factor is 4 (reload register = 3).
Timer/Counter 1 &
Timer/Counter 2
Timer/Counter1, Timer/Counter2 are two general purpose 32-bit timers. They share the same
decrementer. The timer value is then decremented each time the prescaler generates a timer
pulse.
Each timer operation is controlled through a dedicated Timer Control register (TIMCTR). A timer
is enabled/disabled by setting TIMCTRx ENx.
Each time a timer underflows, an interrupt is generated. These interrupts can be masked with
the Interrupt Mask and Priority register (ITMP).
Setting TIMCTRx RLx, the content of the reload register (TIMR) is automatically reloaded in the
Timer Counter register (TIMC) after an underflow and the timer continue running. If the reload bit
is reset, the timer stops running after its first underflow.
Timer Counter can be forced with the Timer Reload value at any time by asserting the load bit
TIMCTRx LDx in the Timer Control register.
Figure 31. Timer/Counter 1/2 Block Diagram
Control Logic
Reload Reg.
Counter Reg.
Control Reg.
=0xFFFFFFFF
count tick
timer interrupts
load
enable/disable
TIMCTRn
TIMRn
TIMCn
Dat
a
Bus
(irq 8 & 9)
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