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參數(shù)資料
| 型號： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁數(shù)： | 88/155頁 |
| 文件大小： | 4139K |
| 代理商： | 5962R0722402VYC |
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38
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
If the application needs more time for IO transfer, it is possible to introduce more delay by acti-
vating the hardware bus ready detection bit MCFG1 IOBRDY. Refer to paragraph “BRDY Wait
Write Protection
Read and write protections are provided to prevent accidental accesses to I/O area. Protection
is controlled through the I/O protection bit MCFG1 IOP.
Bus width
To support applications with low memory and performance requirements, I/O area can be con-
figured for 8-bit operations. The configuration of I/O in 8-bit mode is done programming the I/O
bus width in MCFG1 IOWDH.
In such configuration, I/O device is not accessed by multiple 8-bit accesses as other memory
areas. Only one single access is performed
When the I/O bus is configured as an 8-bit wide bus, data 31 downto 24 shall be used as
interface.
Figure 24.
CS
OE
WE
A
D
IO
OE*
AD
AT697F
A[27:0]
D[31:24]
A[27:0]
WRITE*
IOS*
I/O 8-bit bus width connection
Access Error
An access error can be indicated to the processor asserting the BEXC* signal. If enabled by set-
ting logical one the MCFG1 BEXC, the BEXC* signal is sampled with the data.
Trap 0x01 is taken if an instruction fetch is in progress
Trap 0x09 is taken if a data space is in progress
Trap 0x2B is taken if a data store is in progress
BRDY Wait states
For PROM accesses, for IO accesses and for RAM bank 4, but not for the other RAM banks, it is
possible to introduce additional wait states determined by the peripherals with the BRDY* mech-
anism. This capability can be enabled separatly by the respective configuration bits
MCFG1 PBRDY, MCFG1 IOBRDY and MCFG2 RAMBRDY. If the configuration bit is set to
one, the processor waits before ending the transfer, as long as the BRDY* pin is driven high. If
the configuration bit is set to zero (reset state), the BRDY* pin is ignored.Termination of the
BRDY* induced wait states can be in two different modes:
If MCFG1 ABRDY is set to zero (reset state), BRDY* needs to be asserted zero
synchronously with respect to SDCLK, respecting the setup and hold times t19 and t20
(Refer to section “AC Characteristics”, page 131).The processor will terminate the access at
the rising clock edge immediately following the rising edge during which BRDY* was low by
de-asserting the OE* and the select signal (RAMS*[4], IOS* or ROMS*), as shown in the
figures.
If MCFG1 ABRDY is set to one, BRDY* is double synchronised in the processor, and it can
be asserted asynchronously, without respecting t19 and t20, provided it is asserted low for at
least 1.5 clock cycle. Asynchronous BRDY* timing implies an uncertainty, the access
terminates at the second or third edge after its assertion, and read data needs to be kept
stable until OE* and the select signal (RAMS*[4], IOS* or ROMS*) are de-asserted.
It should be noted that the BRDY* mechanism can be used in addition to the nominal duration of
an access (one or two data cycles depending on the access type) and to the fixed wait states
programmed in the “WS” fields (MCFG2
RAMWWS, MCFG1
PRWWS, MCFG1
IOWS).
Even when BRDY* goes low earlier, the trasaction does not terminate until expiration of the pro-
grammed wait states.
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