參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 143/155頁
文件大?。?/td> 4139K
代理商： 5962R0722402VYC
88
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
12..9
rambs[3:0]
SRAM bank size.
Defines the size of each ram bank
“0000” = 8 Kbyte,
“0001” = 16 Kbyte,
...
“1111” = 256 Mbyte.
7
rambrdy
RAM area bus ready enable.
For RAM Bank 4 (RAMSN[4]). If set to one, a RAM access will be extended until BRDY* is asserted (driven
low).
6
rmw
Read-modify-write.
if set, Enable read-modify-write cycles on sub-word writes to 32-bit areas with common write strobe (no byte
write strobe).
5..4
ramwdh[1:0]
SRAM bus width.
Defines the data with of the SRAMarea:
“00” = 8 bits,
“1X” = 32 bits.
3..2
ramwws[1:0]
SRAM write waitstates.
Defines the number of waitstates during SRAM write cycles:
“00” = 0 waitstate,
“01” = 1 waitstates,
“10” = 2 waitstates,
“11” = 3 waitstates.
1..0
ramrws[1:0]
SRAM read waitstates.
Defines the number of waitstates during SRAM read cycles:
“00” = 0 waitstate,
“01” = 1 waitstates,
“10” = 2 waitstates,
“11” = 3 waitstates.
Table 47. Memory Configuration Register 3 - MCFG3
Address = 0x80000008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
srcrv[14:0]
wb
rb
re
pe
tcb[6:0]
r
r/w
r/w r/w r/w r/w
r/w
11101
xxx xxxx xxxx xxxx
0
x
xxxx xxxx
Bit Number
Mnemonic
Description
26..12
srcrv[14:0]
SDRAM refresh counter reload value.
11
wb
EDAC diagnostic write bypass
10
rb
EDAC diagnostic read bypass
9
re
RAM EDAC enable.
Enable EDAC checking of the RAM area
8
pe
PROM EDAC enable.
Enable EDAC checking of the PROM area. At reset, this bit is initialised with the value of PIO[2]
7..0
tcb[6:0]
Test checkbits.
This field replaces the normal checkbits during store cycles when WB is set. TCB is also loaded with the
memory checkbits during load cycles when RB is set.
Bit Number
Mnemonic
Description
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