參數(shù)資料
型號(hào)： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 141/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
86
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Memory Interface
Registers
Table 45. Memory Configuration Register 1 - MCFG1
Address = 0x80000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
res
e
rv
ed
pbr
dy
abr
dy
iowdh[1:0]
iobrd
y
bexc
res
e
rv
ed
io
ws[3
:0]
io
p
res
e
rv
ed
pr
wen
res
e
rv
ed
prwdh
[1:0]
prwws[3:0]
pr
rws[3:0]
r/w r/w r/w
r/w
r/w r/w r/w
r/w
r/w r/w
r/w
x
0
xx
0
x
xxx
0
xxx xxxx
0
x
xx
1111
Bit Number
Mnemonic
Description
30
pbrdy
PROM area bus ready enable
if set, a PROM access will be extended until BRDY* is asserted (driven low).
29
abrdy
Asynchronous bus ready
If set, the BRDY* input can be asserted without relation to the sysstem clock, provided it is at least 1.5 clock
cycles long. Termination of the access after assertion of BRDY* will be delayed by at least one clock cycle.
28:27
iowdh[1:0]
I/O bus width.
Defines the data with of the I/O area (“00”=8, “10”=32).
26
iobrdy
IO area bus ready enable
if set to one, an IO access will be extended until BRDY* is asserted (Driven low)
25
bexc
Bus error enable for RAM, PROM and IO transactions.
If set to one, the (low) assertion of the BEXC* will generate an error response on the internal bus and causes a
trap (0x01, 0x09, 0x2B) depending on the type of access.
23:20
iows[3:0]
I/O waitstates.
Defines the number of waitstates during I/O accesses:
“0000” = 0 waitstate,
“0001” = 1 waitstates,
...,
“1111” = 15 waitstates.
19
iop
I/O protection.
‘0’ : Read and write accesses to I/O area are disabled
‘1’ : Read and write accesses to I/O area are enabled.
11
prwen
Prom write enable.
If set, enables write cycles to the prom area.
9:8
prwdh[1:0]
Prom width.
Defines the data with of the prom area:
“00” = 8 bits,
“10” = 32 bits.
7..4
prwws[3:0]
Prom write waitstates.
Defines the number of waitstates during prom write cycles:
“0000” = 0 waitstate,
“0001” = 2 waitstates,
...,
“1111” = 30 waitstates.
3..0
prrws[3:0]
Prom read waitstates.
Defines the number of waitstates during prom read cycles
“0000” = 0 waitstate,
“0001” = 2 waitstates,
...,
“1111” = 30waitstates.
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