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參數(shù)資料
| 型號： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁數(shù)： | 35/155頁 |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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13
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
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PCI interface
A/D[31:0] - PCI Address Data (bi-directional)
Address and Data are multiplexed on the same PCI pins.
During the address phase, A/D[31::00] contain a physical address (32 bits). For I/O, this is a byte
address; for configuration and memory, it is a DWORD address. During data phases,
A/D[07::00] contain the least significant byte and A/D[31::24] contain the most significant byte.
C/BE[3:0]* - PCI Bus Command and Byte Enables (bi-directional)
During the address phase of a transaction, C/BE[3::0]* define the bus command. During the data
phase, C/BE[3::0]* are used as Byte Enables. The Byte Enables are valid for the entire data
phase.
PAR - Parity (bi-directional)
The number of "1"s on A/D[31::00], C/BE[3::0]*, and PAR equals an even number
FRAME* - Cycle Frame (bi-directional)
It is driven by the current master to indicate the beginning and duration of an access. FRAME* is
asserted to indicate a bus transaction is beginning. While FRAME* is asserted, data transfers
continue. When FRAME* is deasserted, the transaction is in the final data phase or has
completed.
IRDY* - Initiator Ready (bi-directional)
IRDY* indicates the initiating agent’s ability to complete the current data phase of the transac-
tion. IRDY* is used in conjunction with TRDY*. During a write, IRDY* indicates that valid data is
present on A/D[31::00]. During a read, it indicates the master is prepared to accept data.
TRDY* - Target Ready (bi-directional)
TRDY* indicates the target agent’s (selected device’s) ability to complete the current data phase
of the transaction. TRDY* is used in conjunction with IRDY*. During a read, TRDY* indicates that
valid data is present on AD[31::00]. During a write, it indicates the target is prepared to accept
data.
STOP* - Stop (bi-directional)
STOP* indicates the current target is requesting the master to stop the current transaction.
PCI_LOCK* - Lock (bi-directional)
PCI_LOCK* indicates an atomic operation to a bridge that may require multiple transactions to
complete.
IDSEL - Initialization Device Select (input)
Initialization Device Select is used as a chip select during configuration read and write
transactions.
DEVSEL* - Device Select (bi-directional)
When actively driven, indicates the driving device has decoded its address as the target of the
current access. As an input, DEVSEL* indicates whether any device on the bus has been
selected.
REQ* - PCI bus request (output)
REQ* indicates to the arbiter that this agent desires use of the bus. This is a point-to-point sig-
nal. Every master has its own REQ* which must be tri-stated while RST* is asserted.
GNT* - PCI Bus Grant (input)
GNT* indicates to the agent that access to the bus has been granted. This is a point-to-point sig-
nal. Every master has its own GNT* which must be ignored while RST* is asserted.
PCI_CLK - PCI clock (input)
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相關(guān)代理商/技術(shù)參數(shù) |
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| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
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| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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| 5962R0724902VPC | 制造商:Intersil Corporation 功能描述: |
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